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1. 发明申请

US20160351719A1 THIN FILM TRANSISTOR AND METHOD OF MANUFACTURING SAME 有权
标题翻译：薄膜晶体管及其制造方法
公开(公告)号：US20160351719A1
公开(公告)日：2016-12-01
申请号：US14834608
申请日：2015-08-25
申请人： HON HAI PRECISION INDUSTRY CO., LTD.
发明人： PO-LI SHIH , YI-CHUN KAO , CHIH-LUNG LEE , KUO-LUNG FANG , HSIN-HUA LIN
IPC分类号： H01L29/786 , H01L27/12
CPC分类号： H01L29/78606 , H01L27/1288 , H01L29/66765 , H01L29/66969 , H01L29/78684 , H01L29/7869 , H01L29/78696
摘要： A method for manufacturing a thin film transistor include following steps. A substrate is provided. A gate electrode and an electrically insulating layer are formed on the substrate. An electric conducting layer is formed on the electrically insulating layer. A first photoresist pattern layer is formed on the electric conducting layer. A portion of the electric conducting layer which is not covered by the first photoresist pattern layer is etched to form an electric conduction layer. A semiconductor layer is formed on the electric conduction layer. A second photoresist pattern layer is formed. A portion of the semiconductor layer which is not covered by the second photoresist pattern layer is etched to form the channel layer covering the electric conduction layer. A source electrode and a drain electrode are formed at the two lateral portions of the channel layer respectively. The thin film transistor is also provided.
摘要翻译：制造薄膜晶体管的方法包括以下步骤。提供基板。在基板上形成栅电极和电绝缘层。在电绝缘层上形成导电层。在导电层上形成第一光致抗蚀剂图案层。未被第一光致抗蚀剂图案层覆盖的导电层的一部分被蚀刻以形成导电层。在导电层上形成半导体层。形成第二光致抗蚀剂图案层。蚀刻未被第二光致抗蚀剂图案层覆盖的半导体层的一部分，以形成覆盖导电层的沟道层。源电极和漏电极分别形成在沟道层的两个侧面部分。还提供薄膜晶体管。

2. 发明申请

US20210109092A1 SENSOR USING ULTRASOUND TO DETECT TARGET SUBSTANCE AND DETECTING DEVICE USING SAME 有权
公开(公告)号：US20210109092A1
公开(公告)日：2021-04-15
申请号：US16833904
申请日：2020-03-30
申请人： HON HAI PRECISION INDUSTRY CO., LTD.
发明人： HSIN-HUA LIN , WEI-CHIH CHANG , PO-LI SHIH , CHAO-CHUN YANG , I-MIN LU
IPC分类号： G01N33/53 , G01N29/22 , G01N29/036
摘要： A sensor using ultrasound to detect presence and nature of analyte includes an ultrasonic element and a receptor thereon. The ultrasonic element includes a first electrode, a second electrode facing and spaced apart from the first electrode, an insulating layer between the first electrode and the second electrode, and a vibrating film between the insulating layer and the first electrode. The vibrating film carries the first electrode. A cavity is formed between the vibrating film and the insulating layer. The receptor is on a side of the first electrode away from the second electrode. The receptor can combine with a target substance in a test analyte. When the first electrode and the second electrode are applied with different voltages, certain ultrasound frequencies are generated as the vibrating film vibrates, and the presence and weight of different target substances are indicated by the changes in resonance.

3. 发明申请

US20170207325A1 METHOD FOR FABRICATING CONDUCTING STRUCTURE AND THIN FILM TRANSISTOR ARRAY PANEL 有权
公开(公告)号：US20170207325A1
公开(公告)日：2017-07-20
申请号：US15071170
申请日：2016-03-15
申请人： HON HAI PRECISION INDUSTRY CO., LTD.
发明人： HSIN-HUA LIN , PO-LI SHIH , YI-CHUN KAO , CHANG-CHUN WAN , WEI-CHIH CHANG , I-WEI WU
IPC分类号： H01L29/66 , H01L21/4763 , H01L21/441 , H01L29/24 , H01L29/786 , H01L29/45 , H01L21/477
CPC分类号： H01L29/66969 , H01L21/441 , H01L21/47635 , H01L21/477 , H01L27/124 , H01L29/24 , H01L29/41733 , H01L29/45 , H01L29/458 , H01L29/66765 , H01L29/78669 , H01L29/78678 , H01L29/7869
摘要： A method of providing a conducting structure over a substrate, which comprises: disposing a lower sub-layer over a substrate, the lower sub-layer comprising a conductive metal oxide material that includes indium and zinc, wherein the indium and zinc content in the bottom sub-layer substantially defines a first indium to zinc content ratio; performing a first hydrogen treatment over an exposed surface of the lower sub-layer for introducing hydrogen content therein; disposing a middle sub-layer over the lower sub-layer, the middle sub-layer comprising a metal material; disposing an upper sub-layer over the middle sub-layer, the upper sub-layer comprising a conductive metal oxide material that includes indium and zinc, wherein the indium and the zinc content in the upper sub-layer substantially defines a second indium to zinc content ratio smaller than the first indium to zinc content ratio; and patterning the multi-layered conductive structure to generate a composite lateral etch profile.

4. 发明申请

US20190019870A1 THIN FILM TRANSISTOR ARRAY PANEL AND CONDUCTING STRUCTURE 审中-公开
公开(公告)号：US20190019870A1
公开(公告)日：2019-01-17
申请号：US16069518
申请日：2016-12-07
申请人： HONG FU JIN PRECISION INDUSTRY (ShenZhen) CO., LTD. , HON HAI PRECISION INDUSTRY CO., LTD.
发明人： YI-CHUN KAO , HSIN-HUA LIN , PO-LI SHIH , WEI-CHIH CHANG , I-MIN LU , I-WEI WU
IPC分类号： H01L29/417 , H01L27/12 , H01L29/786 , H01L29/45 , H01L29/66
摘要： A thin film transistor array panel includes a first conductive layer (102) including a gate electrode; a channel layer (104) disposed over the gate; and a second conductive layer (105) disposed over the channel layer (104). The second conductive layer (105) includes a multi-layered portion defining a source electrode (105a) and a drain electrode (105b), which includes a first sub-layer (105-1), a second sub-layer (105-2), and a third sub-layer (105-3) sequentially disposed one over another. Both the third and the first sub-layers (105-3, 105-1) include indium and zinc oxide materials. An indium to zinc content ratio in the first sub-layer (105-1) is greater than that in the third sub-layer (105-3). The content ratio differentiation between the first and the third sub-layers (105-1, 105-3) affects a lateral etch profile associated with a gap (106) generated in the second conductive layer (105) between the source and the drain electrodes (105a, 105b), where the associated gap (106) width in the third sub-layer (105-3) is wider than that in the first sub-layer (105-1).

5. 发明申请

US20180374960A1 TFT SUBSTRATE AND METHOD FOR MAKING SAME 审中-公开
公开(公告)号：US20180374960A1
公开(公告)日：2018-12-27
申请号：US16061653
申请日：2016-12-06
申请人： HONG FU JIN PRECISION INDUSTRY (ShenZhen) CO., LTD. , HON HAI PRECISION INDUSTRY CO., LTD.
发明人： YI-CHUN KAO , PO-LI SHIH , WEI-CHIH CHANG , I-WEI WU
IPC分类号： H01L29/786 , H01L29/04 , H01L29/417 , H01L29/45 , H01L27/12 , H01L21/02 , H01L21/465
摘要： A high-performance TFT substrate (100) for a flat panel display includes a substrate (110), a first conductive layer (130) on the substrate (110), a semiconductor layer (103) positioned on the first conductive layer (130), and a second conductive layer (150) positioned on the semiconductor layer (103). The first conductive layer (130) defines a gate electrode (101). The second conductive layer (150) defines a source electrode (105) and a drain electrode (106) spaced apart from the source electrode (105). The second conductive layer (150) includes a first layer (151) on the semiconductor layer (103) and a second layer (152) positioned on the first layer (151). The first layer (151) can be made of metal oxide. The second layer (152) can be made of aluminum or aluminum alloy.

6. 发明申请

US20160343738A1 THIN FILM TRANSISTOR OF ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF 审中-公开
标题翻译：阵列基片的薄膜晶体管及其制造方法
公开(公告)号：US20160343738A1
公开(公告)日：2016-11-24
申请号：US14833658
申请日：2015-08-24
申请人： HON HAI PRECISION INDUSTRY CO., LTD.
发明人： YI-CHUN KAO , HSIN-HUA LIN , CHIH-LUNG LEE , KUO-LUNG FANG , PO-LI SHIH
IPC分类号： H01L27/12 , H01L21/027 , H01L29/66 , H01L29/786 , H01L29/423
CPC分类号： H01L27/1225 , H01L21/31058 , H01L27/1248 , H01L27/1288 , H01L29/42384 , H01L29/66969 , H01L29/78606 , H01L29/78636 , H01L29/7869
摘要： A method for manufacturing a thin film transistor (TFT), the TFT includes a gate, a first insulation layer, a channel layer, a source, a drain, a second insulation, and a flat layer. The gate is formed on a base. The first insulation layer is formed on the base to cover the gate and the base. The channel layer is formed on the first insulation layer corresponding to the gate. The second insulation layer is formed on the base to cover the first insulation layer, the channel layer, the source, and the drain. The flat layer includes a first region and a second region and is formed on the second insulation layer. The first region and the second region respectively have different light transmittance.
摘要翻译：一种制造薄膜晶体管（TFT）的方法，TFT包括栅极，第一绝缘层，沟道层，源极，漏极，第二绝缘层和平坦层。门形成在基座上。第一绝缘层形成在基座上以覆盖栅极和基底。沟道层形成在对应于栅极的第一绝缘层上。第二绝缘层形成在基底上以覆盖第一绝缘层，沟道层，源极和漏极。平坦层包括第一区域和第二区域，并且形成在第二绝缘层上。第一区域和第二区域分别具有不同的透光率。

7. 发明申请

US20160329362A1 THIN FILM TRANSISTOR AND METHOD OF MAKING SAME 有权
标题翻译：薄膜晶体管及其制造方法
公开(公告)号：US20160329362A1
公开(公告)日：2016-11-10
申请号：US15215911
申请日：2016-07-21
申请人： HON HAI PRECISION INDUSTRY CO., LTD.
发明人： KUO-LUNG FANG , YI-CHUN KAO , HSIN-HUA LIN , CHIH-LUNG LEE , PO-LI SHIH
IPC分类号： H01L27/12 , H01L29/66 , H01L29/786
CPC分类号： H01L27/1288 , H01L27/1225 , H01L29/41733 , H01L29/42384 , H01L29/66742 , H01L29/66765 , H01L29/66969 , H01L29/78618 , H01L29/78678 , H01L29/7869 , H01L29/78696
摘要： A thin film transistor includes a substrate, a gate electrode formed on the substrate, an electrically insulating layer formed on the substrate and covering the gate electrode, a channel layer made of semiconductor material and formed on the electrically insulating layer, an etch stop pattern formed on the channel layer and defining a first through hole and a second through hole; and a source electrode and a drain electrode formed on the etch stop pattern. The source electrode extends into the first through hole to electrically couple to the channel layer. The drain electrode extends into the second through hole to electrically couple to the channel layer. Both the channel layer and the etch stop pattern are formed by using a single mask and a single photoresist layer.
摘要翻译：薄膜晶体管包括基板，形成在基板上的栅电极，形成在基板上并覆盖栅电极的电绝缘层，由半导体材料制成并形成在电绝缘层上的沟道层，形成有蚀刻停止图案在沟道层上形成第一通孔和第二通孔; 以及形成在蚀刻停止图案上的源电极和漏电极。源电极延伸到第一通孔中以电耦合到沟道层。漏电极延伸到第二通孔中以电耦合到沟道层。通过使用单个掩模和单个光致抗蚀剂层来形成通道层和蚀刻停止图案。

8. 发明申请

US20160190341A1 THIN FILM TRANSISTOR AND THIN FILM TRANSISTOR SUBSTRATE 有权
标题翻译：薄膜晶体管和薄膜晶体管基板
公开(公告)号：US20160190341A1
公开(公告)日：2016-06-30
申请号：US14847710
申请日：2015-09-08
申请人： HON HAI PRECISION INDUSTRY CO., LTD.
发明人： KUO-LUNG FANG , PO-LI SHIH , YI-CHUN KAO , HSIN-HUA LIN , CHIH-LUNG LEE
IPC分类号： H01L29/786 , H01L29/417 , H01L27/12
CPC分类号： H01L29/78645 , H01L29/7869 , H01L29/78696
摘要： A thin film transistor includes a first gate electrode located on a base, a second gate electrode located on the base, an insulating layer, a source electrode, a drain electrode, and a channel layer. The insulating layer covers the base, the first gate electrode, and the second gate electrode. The second gate electrode is insulated from the first gate electrode. The channel layer includes a first portion and a second portion sandwiched between the first portion and the insulating layer. A conductivity of the second portion is larger than a conductivity of the first portion. The first portion includes a first region facing the first gate electrode and a second region facing the second gate electrode. The source electrode is electrically connected to the first region, and the drain electrode is electrically connected to the second region.
摘要翻译：薄膜晶体管包括位于基极上的第一栅电极，位于基极上的第二栅电极，绝缘层，源电极，漏电极和沟道层。绝缘层覆盖基极，第一栅电极和第二栅电极。第二栅电极与第一栅电极绝缘。沟道层包括第一部分和夹在第一部分和绝缘层之间的第二部分。第二部分的电导率大于第一部分的电导率。第一部分包括面向第一栅电极的第一区域和面向第二栅电极的第二区域。源极电连接到第一区域，漏极电连接到第二区域。

9. 发明申请

US20160118411A1 TFT ARRAY SUBSTRATE, DISPLAY PANEL, AND TFT STRUCTURE 有权
标题翻译： TFT阵列基板，显示面板和TFT结构
公开(公告)号：US20160118411A1
公开(公告)日：2016-04-28
申请号：US14808594
申请日：2015-07-24
申请人： HON HAI PRECISION INDUSTRY CO., LTD.
发明人： YI-CHUN KAO , HSIN-HUA LIN , PO-LI SHIH , CHIH-LUNG LEE
IPC分类号： H01L27/12
CPC分类号： H01L27/124 , H01L27/1251
摘要： A TFT array substrate includes a plurality of scan lines, a plurality of date lines, a plurality of pixels, a first TFT, and a second TFT. The number of scan lines includes a first scan line. The date lines are insulated with the scan lines include a first date line and a second date line. The first date line is insulated and at least partly covering the second date line. The pixels are defined by two adjacent scan lines and two adjacent date lines. The first TFT is configured to drive a first pixel at the first side of the first scan line and being coupled with the first scan line and the first date line. The second TFT is configured to drive a second pixel at the second side of the first scan line and being coupled with the first scan line and the second date line.
摘要翻译： TFT阵列基板包括多条扫描线，多条日期线，多个像素，第一TFT和第二TFT。扫描线的数量包括第一扫描线。日期行被隔离，扫描线包括第一个日期行和第二个日期行。第一个日期行是绝缘的，至少部分覆盖第二个日期行。像素由两条相邻的扫描线和两条相邻的日期线定义。第一TFT被配置为驱动第一扫描线的第一侧的第一像素并与第一扫描线和第一日期线耦合。第二TFT被配置为驱动第一扫描线的第二侧的第二像素并与第一扫描线和第二日期线耦合。

10. 发明申请

US20200209187A1 GAS SENSOR AND METHOD FOR MAKING SAME 审中-公开
公开(公告)号：US20200209187A1
公开(公告)日：2020-07-02
申请号：US16727632
申请日：2019-12-26
申请人： HON HAI PRECISION INDUSTRY CO., LTD.
发明人： WEI-CHIH CHANG , HSIN-HUA LIN , PO-LI SHIH
IPC分类号： G01N27/414 , H01L29/786 , H01L29/49 , H01L29/66
摘要： A gas sensor with instantaneous electrical response and thus detection of gas which meets it includes a substrate, a bottom gate electrode on a surface of the substrate, an insulating layer on the surface of the substrate carrying the bottom gate electrode and completely covering the bottom gate electrode. A semiconductor layer is on a surface of the insulating layer away from the substrate. Both the source electrode and the drain electrode, spaced apart, are located on a side of the semiconductor layer away from the substrate each being coupled to the semiconductor layer. The gas sensor further includes a passivation layer covering the semiconductor layer and a top gate electrode on the passivation layer, the top gate electrode being spaced from both the source and drain electrodes. The top gate electrode is made of electrically-conductive and gas-sensitive material. A method for making same is also disclosed.

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