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1. 发明申请

US20160242278A1 MULTILAYER WIRING BOARD AND METHOD FOR MANUFACTURING SAME 有权
标题翻译：多层接线板及其制造方法
公开(公告)号：US20160242278A1
公开(公告)日：2016-08-18
申请号：US15027784
申请日：2014-09-24
申请人： HITACHI CHEMICAL COMPANY, LTD.
发明人： Nobuyuki YOSHIDA
IPC分类号： H05K1/02 , H05K3/10 , H05K3/42 , H05K1/11 , H05K3/46
CPC分类号： H05K3/4652 , H05K3/0035 , H05K3/0038 , H05K3/421 , H05K3/422
摘要： The present invention is a multilayer wiring board and a method for manufacturing the same, the multilayer wiring board having a hole for interlayer connection penetrating a metal foil and an insulating layer; an overhang of the metal foil formed at an opening of the hole; lower space formed between the overhang and an inside wall of the hole; and interlayer connection in which the hole is filled with electrolytic filling plating layers, wherein the electrolytic filling plating layers are formed as at least two or more layers, the lower space is filled with any electrolytic filling plating layer except for an outermost layer of the two or more layers of electrolytic filling plating layers, and a diameter in the inside of the interlayer connection formed by any electrolytic filling plating layer except for an outermost layer is equal to or larger than a diameter of the opening.
摘要翻译：本发明是一种多层布线基板及其制造方法，具有贯穿金属箔和绝缘层的层间连接孔的多层布线基板; 形成在孔的开口处的金属箔的突出部; 在所述突出部和所述孔的内壁之间形成的下部空间; 以及其中填充有电解填充镀层的孔的层间连接，其中电解填充镀层形成为至少两层或更多层，下部空间填充有除二者之外的任何电解填充镀层或更多层的电解填充镀层，并且由除了最外层之外的任何电解填充镀层形成的层间连接的内部的直径等于或大于开口的直径。

2. 发明申请

US20160249463A1 METHOD FOR MANUFACTURING MULTILAYER WIRING SUBSTRATE 审中-公开
标题翻译：制造多层布线基板的方法
公开(公告)号：US20160249463A1
公开(公告)日：2016-08-25
申请号：US15027774
申请日：2014-09-24
申请人： HITACHI CHEMICAL COMPANY, LTD.
发明人： Nobuyuki YOSHIDA
IPC分类号： H05K3/46 , H05K3/00 , H05K3/42
CPC分类号： H05K3/4652 , H05K3/0026 , H05K3/0035 , H05K3/0038 , H05K3/422 , H05K3/423 , H05K2201/0355 , H05K2201/0397 , H05K2201/09863 , H05K2201/2072 , H05K2203/1184 , H05K2203/1476
摘要： The present invention is a method for manufacturing a multilayer wiring board having (1) a step of providing with a hole for a via hole, an overhang of a metal foil formed at an opening of the hole, and lower space formed between the overhang and an inside wall of the hole, by using a conformal method or a direct laser method; and (2) a step of filling in the hole by forming electrolytic filling plating layers within the hole and on the metal foil, wherein the filling-in of the hole by the formation of electrolytic filling plating layers in the step (2) is carried out by temporarily decreasing the electric current density of electrolytic filling plating in the middle of the electrolytic filling plating, and increasing it again.
摘要翻译：本发明是一种多层布线板的制造方法，其特征在于，具有（1）具有通孔的孔，形成在所述孔的开口部的金属箔的突出部以及所述突出部和孔的内壁，通过使用保形法或直接激光法; （2）通过在孔内和金属箔上形成电解填充镀层来填充孔的步骤，其中在步骤（2）中通过形成电解填充镀层填充孔，通过暂时降低电解填充电镀中间的电解填充电镀的电流密度，并再次增加。

3. 发明申请

US20160242299A1 METHOD FOR MANUFACTURING MULTILAYER WIRING SUBSTRATE 审中-公开
标题翻译：制造多层布线基板的方法
公开(公告)号：US20160242299A1
公开(公告)日：2016-08-18
申请号：US15027756
申请日：2014-09-24
申请人： HITACHI CHEMICAL COMPANY, LTD.
发明人： Nobuyuki YOSHIDA
IPC分类号： H05K3/42 , H05K3/46 , H05K3/00
CPC分类号： H05K3/423 , H05K3/0026 , H05K3/0035 , H05K3/421 , H05K3/4652 , H05K2201/0355 , H05K2201/09863 , H05K2201/2072 , H05K2203/1184 , H05K2203/1476 , H05K2203/1492
摘要： The present invention is a method for manufacturing a multilayer wiring board having (1) a step of providing with a hole for a via hole from a metal foil for an upper layer wiring pattern to an inner layer wiring pattern by using a conformal method or a direct laser method, and (2) a step of forming a via hole by forming electrolytic filling plating layers in the hole for a via hole, wherein the formation of the electrolytic filling plating layers in the step (2) is carried out by repeating change in electric current density of temporarily decreasing the electric current density of electrolytic filling plating in the middle of the electrolytic filling plating and then increasing it again, two or more times before the electrolytic filling plating layers block an opening of the hole for a via hole.
摘要翻译：本发明是一种多层布线基板的制造方法，其特征在于，具有（1）在上层布线图案的金属箔和内层布线图案之间设置用于通路孔的工序，直接激光法，（2）通孔形成电解填充镀层形成通孔的步骤，其中在步骤（2）中形成电解填充电镀层是通过重复变化进行的在电解填充电镀中间暂时降低电解填充电镀电流密度的电流密度，然后在电解填充电镀层阻挡用于通孔的孔的开口之前再次增加两次或更多次。

4. 发明申请

US20160050769A1 METHOD FOR MANUFACTURING MULTILAYER WIRING SUBSTRATE 有权
标题翻译：制造多层布线基板的方法
公开(公告)号：US20160050769A1
公开(公告)日：2016-02-18
申请号：US14778677
申请日：2014-03-25
申请人： HITACHI CHEMICAL COMPANY, LTD.
发明人： Nobuyuki YOSHIDA
IPC分类号： H05K3/42 , C25D7/12 , C25D5/34 , C25D5/48 , H05K1/02 , C23C18/16 , H05K3/06 , H05K1/03 , H05K1/09 , H05K1/11 , C25D3/38 , C25D5/10
CPC分类号： H05K3/421 , C23C18/1653 , C23C18/405 , C25D3/38 , C25D5/02 , C25D5/10 , C25D5/34 , C25D5/48 , C25D7/00 , C25D7/123 , H05K1/0298 , H05K1/0346 , H05K1/09 , H05K1/115 , H05K3/06 , H05K3/382 , H05K3/427 , H05K3/4652 , H05K3/4661 , H05K2201/0154 , H05K2201/0355 , H05K2201/09545 , H05K2201/09563 , H05K2203/0353 , H05K2203/1423
摘要： To provide a method for manufacturing a multilayer wiring substrate, in which an insulating layer and a metal foil provided thereon are integrally laminated on an inner layer material having a wiring formed thereon, in which a hole for via hole is formed in the metal foil and the insulating layer, and in which the hole for via hole is filled with an electrolytic filled plating layer after a base electroless plating layer is formed, the method being featured in that, after the base electroless plating layer is formed, first, an electrolysis filled plating layer is formed to the extent that the hole for via hole is not completely filled, and then, after the surface of the electrolytic filled plating layer is etched, the hole for via hole is completely filled by an electrolytic filled plating layer.
摘要翻译：为了提供一种制造多层布线基板的方法，其中设置在其上的绝缘层和金属箔一体层压在其上形成有布线的内层材料上，其中在金属箔中形成有用于通孔的孔，绝缘层，在形成基底化学镀层之后，通孔的孔填充有电解填充的镀层，其特征在于，在形成基底化学镀层之后，首先，填充电解液形成电镀层的程度为通孔的孔未完全填充，然后在电解填充镀层的表面被蚀刻后，通孔的孔完全由电解填充镀层填充。

5. 发明申请

US20180084651A1 METHOD FOR MANUFACTURING MULTILAYER WIRING BOARD 审中-公开
公开(公告)号：US20180084651A1
公开(公告)日：2018-03-22
申请号：US15564157
申请日：2015-11-24
申请人： Hitachi Chemical Company, Ltd.
发明人： Nobuyuki YOSHIDA
IPC分类号： H05K3/40 , H05K3/00 , H05K3/46
CPC分类号： H05K3/4076 , C23C18/1653 , C23C18/30 , C23C18/38 , C25D3/38 , C25D5/18 , C25D7/00 , C25D21/12 , H05K3/0026 , H05K3/0038 , H05K3/423 , H05K3/427 , H05K3/4644 , H05K2203/0723 , H05K2203/107 , H05K2203/1476
摘要： A method for manufacturing a multilayer wiring board includes a step (1) and a step (2). The step (1) disposes a hole for through-hole, a squirt of metal foils, and a lower space. The squirt of the metal foils on both the sides of the insulating layer is formed at an opening of the hole for through-hole. The lower space is formed between the squirt of the metal foils and an inner wall of the hole for through-hole. The step (2) plugs up the hole for through-hole by forming an electrolytic filled plating layer at an inside of the hole for through-hole and on the metal foils on both the sides of the insulating layer. The plugging of the hole for through-hole in the step (2) is performed by once decreasing a current density of an electrolytic filled plating in a middle of the electrolytic filled plating and then increasing the current density again.

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