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1. 发明授权

US5426741A Bus event monitor 失效
标题翻译：总线事件监视器
公开(公告)号：US5426741A
公开(公告)日：1995-06-20
申请号：US182531
申请日：1994-01-14
申请人： H. Bruce Butts, Jr. , James N. Leahy , Richard B. Gillett, Jr.
发明人： H. Bruce Butts, Jr. , James N. Leahy , Richard B. Gillett, Jr.
IPC分类号： G06F11/34 , G06F11/00
CPC分类号： G06F11/348 , G06F11/349 , G06F11/3409 , G06F11/3495 , G06F2201/86 , G06F2201/88
摘要： A monitor for monitoring the occurrence of events on the bus (15) of a multiprocessor computer system. The bus event monitor (BEM) includes a dedicated BEM processor (23) and an event counter subsystem (25). During each bus cycle, the BEM (21) captures and interprets the packet of data being transmitted on the bus (15). If the packet represents an event designated by the user to be of interest, a counter associated with the type of packet that was captured and interpreted is incremented by one. More specifically, a field programmable gate array (FPGA), configured by the user, defines the type of events to be counted. When an event to be accounted occurs, the FPGA (33) produces a counter address that is based on the nature of the event, and causes an enable pulse to be generated. The address is applied to the active one of two event counter banks (39a, 39b) via an input crossbar switch (37a). The enable pulse enables the addressed event counter to be incremented by one. The inactive counter bank is available for reading by the dedicated BEM processor (23) while the counters of the active counter bank are being incremented. Preferably, each counter bank contains a large number of counters (e.g., 64K), each having a large capacity (e.g., 32 bit). As a result, a large number of different events can be counted over an indefinitely long period of time.
摘要翻译：一种用于监视多处理器计算机系统的总线（15）上的事件发生的监视器。总线事件监视器（BEM）包括专用BEM处理器（23）和事件计数器子系统（25）。在每个总线周期期间，BEM（21）捕获并解释正在总线（15）上发送的数据的分组。如果分组表示由用户指定为感兴趣的事件，则与捕获和解释的分组类型相关联的计数器增加1。更具体地，由用户配置的现场可编程门阵列（FPGA）定义要计数的事件的类型。当要考虑的事件发生时，FPGA（33）产生基于事件性质的计数器地址，并且产生使能脉冲。通过输入交叉开关（37a）将地址应用于两个事件计数器组（39a，39b）中的活动的一个。使能脉冲使寻址的事件计数器增加1。当活动计数器组的计数器递增时，非活动计数器存储体可供专用BEM处理器（23）读取。优选地，每个计数器存储体包含大量的计数器（例如，64K），每个计数器具有大容量（例如，32位）。因此，大量不同的事件可以无限期地计算在一起。

2. 发明授权

US5416907A Method and apparatus for transferring data processing data transfer sizes 失效
标题翻译：用于传送数据处理数据传输大小的方法和装置
公开(公告)号：US5416907A
公开(公告)日：1995-05-16
申请号：US538656
申请日：1990-06-15
申请人： R. Stephen Polzin , James N. Leahy , Robert E. Willard
发明人： R. Stephen Polzin , James N. Leahy , Robert E. Willard
IPC分类号： G06F13/28 , G06F13/40 , G06F15/17 , G06F3/00 , G06F7/32 , G06F15/04
CPC分类号： G06F15/17 , G06F13/28 , G06F13/4018
摘要： A method and apparatus for optimizing the performance of a multibus data processing system is provided. An I/O controller is coupled to the I/O bus and includes MORE bit setting means for initiating a MORE stream transaction on the I/O bus and for thereafter terminating the MORE stream transaction. An adapter coupling the I/O bus to the system bus, is configured to receive the MORE stream transaction and transfer it to main memory. The adapter includes MORE bit decoding means for identifying the beginning and the end of the MORE stream transaction, and for identifying whether the MORE stream transaction is a READ or WRITE transaction. The adapter also includes a first buffer for receiving data from the I/O bus and transferring the data to the memory in accordance with the memory's full block transfer size, and a second buffer for receiving a full block of data and transferring that data in accordance with the I/O bus transaction limitations. The adapter is capable of invalidating data located in the first buffer and clearing data located in the second buffer in accordance with a discard transaction when the I/O controller fails to properly terminate the MORE stream transaction.
摘要翻译：提供了一种用于优化多机架数据处理系统的性能的方法和装置。 I / O控制器耦合到I / O总线，并且包括更多位设置装置，用于在I / O总线上启动MORE流事务，并且此后终止MORE流事务。将I / O总线耦合到系统总线的适配器被配置为接收MORE流事务并将其传送到主存储器。适配器包括更多位解码装置，用于识别更多流事务的开始和结束，以及用于识别更多流事务是READ还是WRITE事务。适配器还包括用于从I / O总线接收数据并根据存储器的完整块传输大小将数据传送到存储器的第一缓冲器，以及用于接收完整数据块并根据数据传送该数据的第二缓冲器与I / O总线交易限制。当I / O控制器无法正确终止MORE流事务时，适配器能够根据丢弃事务使位于第一缓冲区中的数据无效并清除位于第二缓冲区中的数据。

3. 发明授权

US5029124A Method and apparatus for providing high speed parallel transfer of bursts of data 失效
标题翻译：用于提供数据突发的高速并行传送的方法和装置
公开(公告)号：US5029124A
公开(公告)日：1991-07-02
申请号：US195049
申请日：1988-05-17
申请人： James N. Leahy , Kenneth D. Sills
发明人： James N. Leahy , Kenneth D. Sills
IPC分类号： G06F13/42 , G06F13/28
CPC分类号： G06F13/28
摘要： Method and apparatus for high speed parallel transfer of bursts of data between a device and an external interface bus. A burst mode asynchronous protocol is utilized, in which synchronous bursts of data using DATA VALID signals are followed by an asynchronous handshake using an ACKNOWLEDGE signal. The apparatus includes a burst register for storing and transmitting the data words in a burst, and control logic responsive to DATA VALID and ACKNOWLEDGE signals and providing control signals to operate the burst register.
摘要翻译：用于在设备和外部接口总线之间高速并行传输数据的方法和装置。使用突发模式异步协议，其中使用DATA VALID信号的数据同步脉冲串之后是使用ACKNOWLEDGE信号的异步握手。该装置包括用于在脉冲串中存储和传输数据字的突发寄存器，以及响应于DATA VALID和ACKNOWLEDGE信号的控制逻辑，并提供控制信号以操作突发寄存器。

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