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1. 发明授权

US08656128B2 Aggregate data processing system having multiple overlapping synthetic computers 有权
标题翻译：具有多个重叠合成计算机的综合数据处理系统
公开(公告)号：US08656128B2
公开(公告)日：2014-02-18
申请号：US13599856
申请日：2012-08-30
申请人： Guy L Guthrie , Charles F. Marino , William J. Starke , Derek E. Williams
发明人： Guy L Guthrie , Charles F. Marino , William J. Starke , Derek E. Williams
IPC分类号： G06F12/00
CPC分类号： G06F12/0813 , G06F12/0284 , G06F15/167
摘要： A first SMP computer has first and second processing units and a first system memory pool, a second SMP computer has third and fourth processing units and a second system memory pool, and a third SMP computer has at least fifth and sixth processing units and third, fourth and fifth system memory pools. The fourth system memory pool is inaccessible to the third, fourth and sixth processing units and accessible to at least the second and fifth processing units, and the fifth system memory pool is inaccessible to the first, second and sixth processing units and accessible to at least the fourth and fifth processing units. A first interconnect couples the second processing unit for load-store coherent, ordered access to the fourth system memory pool, and a second interconnect couples the fourth processing unit for load-store coherent, ordered access to the fifth system memory pool.
摘要翻译：第一SMP计算机具有第一和第二处理单元和第一系统存储器池，第二SMP计算机具有第三和第四处理单元和第二系统存储器池，并且第三SMP计算机具有至少第五和第六处理单元，第三SMP计算机具有至少第五和第六处理单元，第四和第五系统内存池。第四系统存储器池对于第三，第四和第六处理单元是不可访问的，并且可访问至少第二和第五处理单元，并且第五系统存储器池对于第一，第二和第六处理单元是不可访问的，并且至少可访问第四和第五处理单元。第一互连耦合第二处理单元，用于对第四系统存储池进行加载存储相关的有序访问，并且第二互连耦合第四处理单元，用于加载存储相关的有序访问到第五系统存储池。

2. 发明申请

US20120324189A1 AGGREGATE DATA PROCESSING SYSTEM HAVING MULTIPLE OVERLAPPING SYNTHETIC COMPUTERS 有权
标题翻译：具有多重叠加合成计算机的综合数据处理系统
公开(公告)号：US20120324189A1
公开(公告)日：2012-12-20
申请号：US13599856
申请日：2012-08-30
申请人： Guy L. Guthrie , Charles F. Marino , William J. Starke , Derek E. Williams
发明人： Guy L. Guthrie , Charles F. Marino , William J. Starke , Derek E. Williams
IPC分类号： G06F12/14
CPC分类号： G06F12/0813 , G06F12/0284 , G06F15/167
摘要： A first SMP computer has first and second processing units and a first system memory pool, a second SMP computer has third and fourth processing units and a second system memory pool, and a third SMP computer has at least fifth and sixth processing units and third, fourth and fifth system memory pools. The fourth system memory pool is inaccessible to the third, fourth and sixth processing units and accessible to at least the second and fifth processing units, and the fifth system memory pool is inaccessible to the first, second and sixth processing units and accessible to at least the fourth and fifth processing units. A first interconnect couples the second processing unit for load-store coherent, ordered access to the fourth system memory pool, and a second interconnect couples the fourth processing unit for load-store coherent, ordered access to the fifth system memory pool.
摘要翻译：第一SMP计算机具有第一和第二处理单元和第一系统存储器池，第二SMP计算机具有第三和第四处理单元和第二系统存储器池，并且第三SMP计算机具有至少第五和第六处理单元，第三SMP计算机具有至少第五和第六处理单元，第四和第五系统内存池。第四系统存储器池对于第三，第四和第六处理单元是不可访问的，并且可访问至少第二和第五处理单元，并且第五系统存储器池对于第一，第二和第六处理单元是不可访问的，并且至少可访问第四和第五处理单元。第一互连耦合第二处理单元，用于对第四系统存储池进行加载存储相关的有序访问，并且第二互连耦合第四处理单元，用于加载存储相关的有序访问到第五系统存储池。

3. 发明申请

US20110153943A1 Aggregate Data Processing System Having Multiple Overlapping Synthetic Computers 有权
标题翻译：具有多重重合成计算机的综合数据处理系统
公开(公告)号：US20110153943A1
公开(公告)日：2011-06-23
申请号：US12643800
申请日：2009-12-21
申请人： Guy L. Guthrie , Charles F. Marino , William J. Starke , Derek E. Williams
发明人： Guy L. Guthrie , Charles F. Marino , William J. Starke , Derek E. Williams
IPC分类号： G06F12/00 , G06F12/14 , G06F12/08
CPC分类号： G06F12/0813 , G06F12/0284 , G06F15/167
摘要： A first SMP computer has first and second processing units and a first system memory pool, a second SMP computer has third and fourth processing units and a second system memory pool, and a third SMP computer has at least fifth and sixth processing units and third, fourth and fifth system memory pools. The fourth system memory pool is inaccessible to the third, fourth and sixth processing units and accessible to at least the second and fifth processing units, and the fifth system memory pool is inaccessible to the first, second and sixth processing units and accessible to at least the fourth and fifth processing units. A first interconnect couples the second processing unit for load-store coherent, ordered access to the fourth system memory pool, and a second interconnect couples the fourth processing unit for load-store coherent, ordered access to the fifth system memory pool.
摘要翻译：第一SMP计算机具有第一和第二处理单元和第一系统存储器池，第二SMP计算机具有第三和第四处理单元和第二系统存储器池，并且第三SMP计算机具有至少第五和第六处理单元，第三SMP计算机具有至少第五和第六处理单元，第四和第五系统内存池。第四系统存储器池对于第三，第四和第六处理单元是不可访问的，并且可访问至少第二和第五处理单元，并且第五系统存储器池对于第一，第二和第六处理单元是不可访问的，并且至少可访问第四和第五处理单元。第一互连耦合第二处理单元，用于对第四系统存储池进行加载存储相关的有序访问，并且第二互连耦合第四处理单元，用于加载存储相关的有序访问到第五系统存储池。

4. 发明授权

US08370595B2 Aggregate data processing system having multiple overlapping synthetic computers 有权
标题翻译：具有多个重叠合成计算机的综合数据处理系统
公开(公告)号：US08370595B2
公开(公告)日：2013-02-05
申请号：US12643800
申请日：2009-12-21
申请人： Guy L. Guthrie , Charles F. Marino , William J. Starke , Derek E. Williams
发明人： Guy L. Guthrie , Charles F. Marino , William J. Starke , Derek E. Williams
IPC分类号： G06F12/00
CPC分类号： G06F12/0813 , G06F12/0284 , G06F15/167
摘要： A first SMP computer has first and second processing units and a first system memory pool, a second SMP computer has third and fourth processing units and a second system memory pool, and a third SMP computer has at least fifth and sixth processing units and third, fourth and fifth system memory pools. The fourth system memory pool is inaccessible to the third, fourth and sixth processing units and accessible to at least the second and fifth processing units, and the fifth system memory pool is inaccessible to the first, second and sixth processing units and accessible to at least the fourth and fifth processing units. A first interconnect couples the second processing unit for load-store coherent, ordered access to the fourth system memory pool, and a second interconnect couples the fourth processing unit for load-store coherent, ordered access to the fifth system memory pool.
摘要翻译：第一SMP计算机具有第一和第二处理单元和第一系统存储器池，第二SMP计算机具有第三和第四处理单元和第二系统存储器池，并且第三SMP计算机具有至少第五和第六处理单元，第三SMP计算机具有至少第五和第六处理单元，第四和第五系统内存池。第四系统存储器池对于第三，第四和第六处理单元是不可访问的，并且可访问至少第二和第五处理单元，并且第五系统存储器池对于第一，第二和第六处理单元是不可访问的，并且至少可访问第四和第五处理单元。第一互连耦合第二处理单元，用于对第四系统存储池进行加载存储相关的有序访问，并且第二互连耦合第四处理单元，用于加载存储相关的有序访问到第五系统存储池。

5. 发明授权

US08893126B2 Binding a process to a special purpose processing element having characteristics of a processor 有权
标题翻译：将过程绑定到具有处理器特征的专用处理元件
公开(公告)号：US08893126B2
公开(公告)日：2014-11-18
申请号：US12024220
申请日：2008-02-01
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Guy L. Guthrie , Charles F. Marino , William J. Starke
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Guy L. Guthrie , Charles F. Marino , William J. Starke
IPC分类号： G06F9/00 , G06F13/12
CPC分类号： G06F13/12
摘要： A heterogeneous processing element model is provided where I/O devices look and act like processors. In order to be treated like a processor, an I/O processing element, or other special purpose processing element, must follow some rules and have some characteristics of a processor, such as address translation, security, interrupt handling, and exception processing, for example. The heterogeneous processing element model puts special purpose processing elements on the same playing field as processors, from a programming perspective, operating system perspective, and power perspective. The operating system can get work to a security engine, for example, in the same way it does to a processor.
摘要翻译：提供异构处理元件模型，其中I / O设备看起来像处理器一样操作。为了像处理器一样处理I / O处理元件或其他专用处理元件，必须遵循一些规则并具有处理器的某些特性，例如地址转换，安全性，中断处理和异常处理，用于例。异构处理元素模型将特殊处理元素与编程角度，操作系统角度和功能视角相结合，将处理器与处理器相同。操作系统可以使用安全引擎，例如，与处理器相同。

6. 发明申请

US20090198971A1 Heterogeneous Processing Elements 有权
标题翻译：异构处理元件
公开(公告)号：US20090198971A1
公开(公告)日：2009-08-06
申请号：US12024220
申请日：2008-02-01
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Guy L. Guthrie , Charles F. Marino , William J. Starke
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Guy L. Guthrie , Charles F. Marino , William J. Starke
IPC分类号： G06F9/30
CPC分类号： G06F13/12
摘要： A heterogeneous processing element model is provided where I/O devices look and act like processors. In order to be treated like a processor, an I/O processing element, or other special purpose processing element, must follow some rules and have some characteristics of a processor, such as address translation, security, interrupt handling, and exception processing, for example. The heterogeneous processing element model puts special purpose processing elements on the same playing field as processors, from a programming perspective, operating system perspective, power perspective, as the processors. The operating system can get work to a security engine, for example, in the same way it does to a processor.
摘要翻译：提供异构处理元件模型，其中I / O设备看起来像处理器一样操作。为了像处理器一样处理I / O处理元件或其他专用处理元件，必须遵循一些规则并具有处理器的某些特性，例如地址转换，安全性，中断处理和异常处理，用于例。异构处理元素模型将特殊处理元素放在与处理器相同的竞争环境中，从编程角度，操作系统的角度，功率视角，作为处理器。操作系统可以使用安全引擎，例如，与处理器相同。

7. 发明申请

US20130205120A1 PROCESSOR PERFORMANCE IMPROVEMENT FOR INSTRUCTION SEQUENCES THAT INCLUDE BARRIER INSTRUCTIONS 有权
标题翻译：包括障碍指示的指令序列的处理器性能改进
公开(公告)号：US20130205120A1
公开(公告)日：2013-08-08
申请号：US13369029
申请日：2012-02-08
申请人： Guy L Guthrie , William J. Starke , Derek E Williams
发明人： Guy L Guthrie , William J. Starke , Derek E Williams
IPC分类号： G06F9/312
CPC分类号： G06F9/52 , G06F9/30087 , G06F9/30145 , G06F9/3834 , G06F12/0831
摘要： A technique for processing an instruction sequence that includes a barrier instruction, a load instruction preceding the barrier instruction, and a subsequent memory access instruction following the barrier instruction includes determining that the load instruction is resolved based upon receipt of an earliest of a good combined response for a read operation corresponding to the load instruction and data for the load instruction. The technique also includes if execution of the subsequent memory access instruction is not initiated prior to completion of the barrier instruction, initiating in response to determining the barrier instruction completed, execution of the subsequent memory access instruction. The technique further includes if execution of the subsequent memory access instruction is initiated prior to completion of the barrier instruction, discontinuing in response to determining the barrier instruction completed, tracking of the subsequent memory access instruction with respect to invalidation.
摘要翻译：一种用于处理指示序列的技术，该指令序列包括屏障指令，屏障指令之前的加载指令，以及跟随障碍指令之后的随后存储器访问指令，包括：基于接收到最早的良好组合响应来确定加载指令是否被解决用于与加载指令相对应的读取操作和用于加载指令的数据。该技术还包括如果在完成屏障指令之前没有启动后续存储器访问指令的执行，则响应于确定完成的屏障指令启动后续存储器访问指令的执行。该技术还包括如果在完成屏障指令之前启动后续存储器访问指令的执行，则响应于确定所完成的屏障指令而中断，跟踪关于无效的后续存储器访问指令。

8. 发明授权

US08495308B2 Processor, data processing system and method supporting a shared global coherency state 失效
标题翻译：处理器，数据处理系统和支持共享全局一致性状态的方法
公开(公告)号：US08495308B2
公开(公告)日：2013-07-23
申请号：US11539694
申请日：2006-10-09
申请人： Guy L. Guthrie , William J. Starke , Derek E. Williams , Phillip G. Williams
发明人： Guy L. Guthrie , William J. Starke , Derek E. Williams , Phillip G. Williams
IPC分类号： G06F12/00
CPC分类号： G06F12/0831 , G06F12/0817
摘要： A multiprocessor data processing system includes at least first and second coherency domains, where the first coherency domain includes a system memory and a cache memory. According to a method of data processing, a cache line is buffered in a data array of the cache memory and a state field in a cache directory of the cache memory is set to a coherency state to indicate that the cache line is valid in the data array, that the cache line is held in the cache memory non-exclusively, and that another cache in said second coherency domain may hold a copy of the cache line.
摘要翻译：多处理器数据处理系统至少包括第一和第二相干域，其中第一相干域包括系统存储器和高速缓冲存储器。根据数据处理的方法，将高速缓存行缓冲在高速缓冲存储器的数据阵列中，高速缓冲存储器的高速缓存目录中的状态字段被设置为一致性状态，以指示高速缓存行在数据中是有效的数组，高速缓存存储器行被非排他地保存在高速缓冲存储器中，并且所述第二相干域中的另一个高速缓冲存储器可以保存高速缓存行的副本。

9. 发明申请

US20110047352A1 MEMORY COHERENCE DIRECTORY SUPPORTING REMOTELY SOURCED REQUESTS OF NODAL SCOPE 失效
标题翻译：记忆协调指导原则支持远程请求的NODAL范围
公开(公告)号：US20110047352A1
公开(公告)日：2011-02-24
申请号：US12545246
申请日：2009-08-21
申请人： Paul A. Ganfield , Guy L. Guthrie , David J. Krolak , Michael S. Siegel , William J. Starke , Jeffrey A. Stuecheli , Derek E. Williams
发明人： Paul A. Ganfield , Guy L. Guthrie , David J. Krolak , Michael S. Siegel , William J. Starke , Jeffrey A. Stuecheli , Derek E. Williams
IPC分类号： G06F15/76 , G06F9/02 , G06F12/08
CPC分类号： G06F12/0817
摘要： A data processing system includes at least a first through third processing nodes coupled by an interconnect fabric. The first processing node includes a master, a plurality of snoopers capable of participating in interconnect operations, and a node interface that receives a request of the master and transmits the request of the master to the second processing unit with a nodal scope of transmission limited to the second processing node. The second processing node includes a node interface having a directory. The node interface of the second processing node permits the request to proceed with the nodal scope of transmission if the directory does not indicate that a target memory block of the request is cached other than in the second processing node and prevents the request from succeeding if the directory indicates that the target memory block of the request is cached other than in the second processing node.
摘要翻译：数据处理系统至少包括通过互连结构耦合的第一至第三处理节点。第一处理节点包括主机，能够参与互连操作的多个侦听器，以及接收主机请求的节点接口，并将主机的请求传送到第二处理单元，传送范围限于第二处理节点。第二处理节点包括具有目录的节点接口。第二处理节点的节点接口允许请求继续进行节点传输范围，如果该目录没有指示该请求的目标存储器块不是在第二处理节点中被缓存，并且如果该请求成功目录指示除第二处理节点之外的请求的目标存储块被缓存。

10. 发明申请

US20100257317A1 Virtual Barrier Synchronization Cache 失效
标题翻译：虚拟障碍同步缓存
公开(公告)号：US20100257317A1
公开(公告)日：2010-10-07
申请号：US12419364
申请日：2009-04-07
申请人： Ravi K. Arimilli , Guy L. Guthrie , Robert A. Cargnoni , William J. Starke , Derek E. Williams
发明人： Ravi K. Arimilli , Guy L. Guthrie , Robert A. Cargnoni , William J. Starke , Derek E. Williams
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0811 , G06F9/522
摘要： A data processing system includes an interconnect fabric, a system memory coupled to the interconnect fabric and including a virtual barrier synchronization region allocated to storage of virtual barrier synchronization registers (VBSRs), and a plurality of processing units coupled to the interconnect fabric and operable to access the virtual barrier synchronization region of the system memory. Each of the plurality of processing units includes a processor core and a cache memory including a cache array that caches VBSR lines from the virtual barrier synchronization region of the system memory and a cache controller. The cache controller, responsive to a store request from the processor core to update a particular VBSR line, performs a non-blocking update of the cache array in each other of the plurality of processing units contemporaneously holding a copy of the particular VBSR line by transmitting a VBSR update command on the interconnect fabric.
摘要翻译：数据处理系统包括互连结构，耦合到互连结构并包括分配给虚拟屏障同步寄存器（VBSR）的存储的虚拟屏障同步区域的系统存储器，以及耦合到互连结构的多个处理单元，访问系统内存的虚拟屏障同步区域。多个处理单元中的每一个包括处理器核心和高速缓存存储器，其包括从系统存储器的虚拟屏障同步区域缓存VBSR行的缓存阵列和高速缓存控制器。高速缓存控制器响应于来自处理器核心的存储请求来更新特定VBSR线路，通过发送来同时保存特定VBSR线路的副本的多个处理单元中的彼此之间的高速缓存阵列的非阻塞更新互连结构上的VBSR更新命令。

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