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1. 发明授权

US08656128B2 Aggregate data processing system having multiple overlapping synthetic computers 有权
标题翻译：具有多个重叠合成计算机的综合数据处理系统
公开(公告)号：US08656128B2
公开(公告)日：2014-02-18
申请号：US13599856
申请日：2012-08-30
申请人： Guy L Guthrie , Charles F. Marino , William J. Starke , Derek E. Williams
发明人： Guy L Guthrie , Charles F. Marino , William J. Starke , Derek E. Williams
IPC分类号： G06F12/00
CPC分类号： G06F12/0813 , G06F12/0284 , G06F15/167
摘要： A first SMP computer has first and second processing units and a first system memory pool, a second SMP computer has third and fourth processing units and a second system memory pool, and a third SMP computer has at least fifth and sixth processing units and third, fourth and fifth system memory pools. The fourth system memory pool is inaccessible to the third, fourth and sixth processing units and accessible to at least the second and fifth processing units, and the fifth system memory pool is inaccessible to the first, second and sixth processing units and accessible to at least the fourth and fifth processing units. A first interconnect couples the second processing unit for load-store coherent, ordered access to the fourth system memory pool, and a second interconnect couples the fourth processing unit for load-store coherent, ordered access to the fifth system memory pool.
摘要翻译：第一SMP计算机具有第一和第二处理单元和第一系统存储器池，第二SMP计算机具有第三和第四处理单元和第二系统存储器池，并且第三SMP计算机具有至少第五和第六处理单元，第三SMP计算机具有至少第五和第六处理单元，第四和第五系统内存池。第四系统存储器池对于第三，第四和第六处理单元是不可访问的，并且可访问至少第二和第五处理单元，并且第五系统存储器池对于第一，第二和第六处理单元是不可访问的，并且至少可访问第四和第五处理单元。第一互连耦合第二处理单元，用于对第四系统存储池进行加载存储相关的有序访问，并且第二互连耦合第四处理单元，用于加载存储相关的有序访问到第五系统存储池。

2. 发明授权

US08935513B2 Processor performance improvement for instruction sequences that include barrier instructions 有权
标题翻译：包括屏障指令的指令序列的处理器性能改善
公开(公告)号：US08935513B2
公开(公告)日：2015-01-13
申请号：US13369029
申请日：2012-02-08
申请人： Guy L Guthrie , William J Starke , Derek E Williams
发明人： Guy L Guthrie , William J Starke , Derek E Williams
IPC分类号： G06F9/52
CPC分类号： G06F9/52 , G06F9/30087 , G06F9/30145 , G06F9/3834 , G06F12/0831
摘要： A technique for processing an instruction sequence that includes a barrier instruction, a load instruction preceding the barrier instruction, and a subsequent memory access instruction following the barrier instruction includes determining that the load instruction is resolved based upon receipt of an earliest of a good combined response for a read operation corresponding to the load instruction and data for the load instruction. The technique also includes if execution of the subsequent memory access instruction is not initiated prior to completion of the barrier instruction, initiating in response to determining the barrier instruction completed, execution of the subsequent memory access instruction. The technique further includes if execution of the subsequent memory access instruction is initiated prior to completion of the barrier instruction, discontinuing in response to determining the barrier instruction completed, tracking of the subsequent memory access instruction with respect to invalidation.
摘要翻译：一种用于处理指示序列的技术，该指令序列包括屏障指令，屏障指令之前的加载指令，以及跟随障碍指令之后的随后存储器访问指令，包括：基于接收到最早的良好组合响应来确定加载指令是否被解决用于与加载指令相对应的读取操作和用于加载指令的数据。该技术还包括如果在完成屏障指令之前没有启动后续存储器访问指令的执行，则响应于确定完成的屏障指令启动后续存储器访问指令的执行。该技术还包括如果在完成屏障指令之前启动后续存储器访问指令的执行，则响应于确定所完成的屏障指令而中断，跟踪关于无效的后续存储器访问指令。

3. 发明申请

US20130205120A1 PROCESSOR PERFORMANCE IMPROVEMENT FOR INSTRUCTION SEQUENCES THAT INCLUDE BARRIER INSTRUCTIONS 有权
标题翻译：包括障碍指示的指令序列的处理器性能改进
公开(公告)号：US20130205120A1
公开(公告)日：2013-08-08
申请号：US13369029
申请日：2012-02-08
申请人： Guy L Guthrie , William J. Starke , Derek E Williams
发明人： Guy L Guthrie , William J. Starke , Derek E Williams
IPC分类号： G06F9/312
CPC分类号： G06F9/52 , G06F9/30087 , G06F9/30145 , G06F9/3834 , G06F12/0831
摘要： A technique for processing an instruction sequence that includes a barrier instruction, a load instruction preceding the barrier instruction, and a subsequent memory access instruction following the barrier instruction includes determining that the load instruction is resolved based upon receipt of an earliest of a good combined response for a read operation corresponding to the load instruction and data for the load instruction. The technique also includes if execution of the subsequent memory access instruction is not initiated prior to completion of the barrier instruction, initiating in response to determining the barrier instruction completed, execution of the subsequent memory access instruction. The technique further includes if execution of the subsequent memory access instruction is initiated prior to completion of the barrier instruction, discontinuing in response to determining the barrier instruction completed, tracking of the subsequent memory access instruction with respect to invalidation.
摘要翻译：一种用于处理指示序列的技术，该指令序列包括屏障指令，屏障指令之前的加载指令，以及跟随障碍指令之后的随后存储器访问指令，包括：基于接收到最早的良好组合响应来确定加载指令是否被解决用于与加载指令相对应的读取操作和用于加载指令的数据。该技术还包括如果在完成屏障指令之前没有启动后续存储器访问指令的执行，则响应于确定完成的屏障指令启动后续存储器访问指令的执行。该技术还包括如果在完成屏障指令之前启动后续存储器访问指令的执行，则响应于确定所完成的屏障指令而中断，跟踪关于无效的后续存储器访问指令。

4. 发明授权

US08799588B2 Forward progress mechanism for stores in the presence of load contention in a system favoring loads by state alteration 有权
公开(公告)号：US08799588B2
公开(公告)日：2014-08-05
申请号：US13368987
申请日：2012-02-08
申请人： Guy L Guthrie , Hien M Le , Hugh Shen , Jeff A Stuecheli , Derek E Williams
发明人： Guy L Guthrie , Hien M Le , Hugh Shen , Jeff A Stuecheli , Derek E Williams
IPC分类号： G06F12/00
CPC分类号： G06F12/0831 , G06F2212/1008 , G06F2212/1016
摘要： A multiprocessor data processing system includes a plurality of cache memories including a cache memory. The cache memory issues a read-type operation for a target cache line. While waiting for receipt of the target cache line, the cache memory monitors to detect a competing store-type operation for the target cache line. In response to receiving the target cache line, the cache memory installs the target cache line in the cache memory, and sets a coherency state of the target cache line installed in the cache memory based on whether the competing store-type operation is detected.

5. 发明授权

US08793442B2 Forward progress mechanism for stores in the presence of load contention in a system favoring loads 有权
标题翻译：在有利于负载的系统中存在负载争用的商店的前进进度机制
公开(公告)号：US08793442B2
公开(公告)日：2014-07-29
申请号：US13368958
申请日：2012-02-08
申请人： Guy L Guthrie , Hien M Le , Jeff A Stuecheli , Derek E Williams
发明人： Guy L Guthrie , Hien M Le , Jeff A Stuecheli , Derek E Williams
IPC分类号： G06F12/00
CPC分类号： G06F12/0897 , G06F12/0811
摘要： A multiprocessor data processing system includes a plurality of cache memories including a cache memory. In response to the cache memory detecting a storage-modifying operation specifying a same target address as that of a first read-type operation being processed by the cache memory, the cache memory provides a retry response to the storage-modifying operation. In response to completion of the read-type operation, the cache memory enters a referee mode. While in the referee mode, the cache memory temporarily dynamically increases priority of any storage-modifying operation targeting the target address in relation to any second read-type operation targeting the target address.
摘要翻译：多处理器数据处理系统包括包括高速缓存存储器的多个高速缓存存储器。响应于高速缓冲存储器检测指定与由高速缓冲存储器处理的第一读取型操作相同的目标地址的存储修改操作，高速缓冲存储器为存储修改操作提供重试响应。响应于完成读取型操作，缓存存储器进入裁判模式。在裁判模式下，高速缓存存储器临时动态地增加针对目标地址的任何存储修改操作的优先级，这相对于针对目标地址的任何第二读取类型操作。

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