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1. 发明授权

US5335138A High dielectric constant capacitor and method of manufacture 失效
标题翻译：高介电常数电容器及其制造方法
公开(公告)号：US5335138A
公开(公告)日：1994-08-02
申请号：US17385
申请日：1993-02-12
申请人： Gurtej Sandhu , Pierre Fazan
发明人： Gurtej Sandhu , Pierre Fazan
IPC分类号： H01L21/02 , H01L27/108 , H01G1/01 , H01L27/00
CPC分类号： H01L28/55 , H01L27/10808 , H01L28/60 , H01L28/75
摘要： A high storage capacity capacitor for a semiconductor structure includes a barrier layer formed on a polysilicon electrode, a lower electrode, a dielectric layer, and an upper electrode. The dielectric material is formed of a high dielectric constant material such as BaSrTiO.sub.3. In order to protect the barrier layer from oxidation during deposition of the dielectric layer and to provide a smooth surface geometry for depositing the dielectric layer, conducting or insulating spacers are formed on the sidewalls of the barrier layer and lower electrode. A smooth dielectric layer can thus be formed that is less susceptible to current leakage. In addition, the insulating spacers can be formed to completely fill a space between adjacent capacitors and to provide a completely planar surface.
摘要翻译：用于半导体结构的高存储容量电容器包括形成在多晶硅电极，下电极，电介质层和上电极上的阻挡层。介电材料由高介电常数材料如BaSrTiO3形成。为了在沉积介电层期间保护阻挡层不被氧化，并且为了沉积电介质层提供平滑的表面几何形状，在阻挡层和下电极的侧壁上形成导电或绝缘间隔物。因此可以形成较不易受电流泄漏影响的平滑介电层。此外，绝缘间隔物可以形成为完全填充相邻电容器之间的空间并提供完全平坦的表面。

2. 发明申请

US20070102705A1 Thin film transistors and semiconductor constructions 失效
标题翻译：薄膜晶体管和半导体结构
公开(公告)号：US20070102705A1
公开(公告)日：2007-05-10
申请号：US11644863
申请日：2006-12-21
申请人： Gurtej Sandhu , Shubneesh Batra , Pierre Fazan
发明人： Gurtej Sandhu , Shubneesh Batra , Pierre Fazan
IPC分类号： H01L29/04 , H01L29/786
CPC分类号： H01L29/78678 , H01L27/1214 , H01L27/127 , H01L29/04 , H01L29/6675 , H01L29/66757 , H01L29/66765 , H01L29/78672 , H01L29/78675
摘要： A method of forming a thin film transistor relative to a substrate includes, a) providing a thin film transistor layer of polycrystalline material on a substrate, the polycrystalline material comprising grain boundaries; b) providing a fluorine containing layer adjacent the polycrystalline thin film layer; c) annealing the fluorine containing layer at a temperature and for a time period which in combination are effective to drive fluorine from the fluorine containing layer into the polycrystalline thin film layer and incorporate fluorine within the grain boundaries to passivate said grain boundaries; and d) providing a transistor gate operatively adjacent the thin film transistor layer. The thin film transistor can be fabricated to be bottom gated or top gated. A buffering layer can be provided intermediate the thin film transistor layer and the fluorine containing layer, with the buffering layer being transmissive of fluorine from the fluorine containing layer during the annealing. Preferably, the annealing temperature is both sufficiently high to drive fluorine from the fluorine containing layer into the polycrystalline thin film layer and incorporate fluorine within the grain boundaries to passivate said grain boundaries, but sufficiently low to prevent chemical reaction of the fluorine containing layer with the polycrystalline thin film layer.
摘要翻译：相对于衬底形成薄膜晶体管的方法包括：a）在衬底上提供多晶材料的薄膜晶体管层，所述多晶材料包括晶界; b）在多晶薄膜层附近提供含氟层; c）在一段温度和一段时间内退火含氟层，所述时间段有效地将氟从含氟层驱动到多晶薄膜层中，并且在晶界内引入氟以钝化所述晶界; 以及d）提供与所述薄膜晶体管层可操作地相邻的晶体管栅极。薄膜晶体管可以被制造为底部门控或顶部门控。可以在薄膜晶体管层和含氟层之间设置缓冲层，缓冲层在退火期间从含氟层透过氟。优选地，退火温度足够高以将氟从含氟层驱动到多晶薄膜层中并且在晶界内引入氟以使所述晶界钝化，但是足够低以防止含氟层与多晶薄膜层。

3. 发明申请

US20060001019A1 Capacitor compatible with high dielectric constant materials having a low contact resistance layer and the method for forming same 有权
公开(公告)号：US20060001019A1
公开(公告)日：2006-01-05
申请号：US11216415
申请日：2005-08-30
申请人： Gurtej Sandhu , Pierre Fazan
发明人： Gurtej Sandhu , Pierre Fazan
IPC分类号： H01L29/06 , H01L29/08
CPC分类号： H01L21/7687 , H01L21/76846 , H01L21/76849 , H01L21/76855 , H01L21/76895 , H01L27/10852 , H01L27/10855 , H01L27/11502 , H01L27/11507 , H01L28/55 , H01L28/60 , H01L28/75
摘要： A storage cell capacitor and a method for forming the storage cell capacitor having a storage node electrode including a barrier layer interposed between a conductive plug and an oxidation resistant layer. A layer of titanium silicide is fabricated to lie between the conductive plug and the oxidation resistant layer. An insulative layer protects the sidewalls of the barrier layer during the deposition and anneal of a dielectric layer having a high dielectric constant.

4. 发明申请

US20050156240A1 Thin film transistors and semiconductor constructions 失效
标题翻译：薄膜晶体管和半导体结构
公开(公告)号：US20050156240A1
公开(公告)日：2005-07-21
申请号：US11021651
申请日：2004-12-22
申请人： Gurtej Sandhu , Shubneesh Batra , Pierre Fazan
发明人： Gurtej Sandhu , Shubneesh Batra , Pierre Fazan
IPC分类号： H01L21/336 , H01L21/77 , H01L21/84 , H01L29/04 , H01L29/786 , H01L21/00 , H01L21/8242
CPC分类号： H01L29/78678 , H01L27/1214 , H01L27/127 , H01L29/04 , H01L29/6675 , H01L29/66757 , H01L29/66765 , H01L29/78672 , H01L29/78675
摘要： A method of forming a thin film transistor relative to a substrate includes, a) providing a thin film transistor layer of polycrystalline material on a substrate, the polycrystalline material comprising grain boundaries; b) providing a fluorine containing layer adjacent the polycrystalline thin film layer; c) annealing the fluorine containing layer at a temperature and for a time period which in combination are effective to drive fluorine from the fluorine containing layer into the polycrystalline thin film layer and incorporate fluorine within the grain boundaries to passivate said grain boundaries; and d) providing a transistor gate operatively adjacent the thin film transistor layer. The thin film transistor can be fabricated to be bottom gated or top gated. A buffering layer can be provided intermediate the thin film transistor layer and the fluorine containing layer, with the buffering layer being transmissive of fluorine from the fluorine containing layer during the annealing. Preferably, the annealing temperature is both sufficiently high to drive fluorine from the fluorine containing layer into the polycrystalline thin film layer and incorporate fluorine within the grain boundaries to passivate said grain boundaries, but sufficiently low to prevent chemical reaction of the fluorine containing layer with the polycrystalline thin film layer.
摘要翻译：相对于衬底形成薄膜晶体管的方法包括：a）在衬底上提供多晶材料的薄膜晶体管层，所述多晶材料包括晶界; b）在多晶薄膜层附近提供含氟层; c）在一段温度和一段时间内退火含氟层，所述时间段有效地将氟从含氟层驱动到多晶薄膜层中，并且在晶界内引入氟以钝化所述晶界; 以及d）提供与所述薄膜晶体管层可操作地相邻的晶体管栅极。薄膜晶体管可以被制造为底部门控或顶部门控。可以在薄膜晶体管层和含氟层之间设置缓冲层，缓冲层在退火期间从含氟层透过氟。优选地，退火温度足够高以将氟从含氟层驱动到多晶薄膜层中并且在晶界内引入氟以使所述晶界钝化，但是足够低以防止含氟层与多晶薄膜层。

5. 发明授权

US08299514B2 High density integrated circuitry for semiconductor memory having memory cells with a minimum capable photolithographic feature dimension 失效
标题翻译：用于半导体存储器的高密度集成电路具有具有最小能力光刻特征尺寸的存储单元
公开(公告)号：US08299514B2
公开(公告)日：2012-10-30
申请号：US13285182
申请日：2011-10-31
申请人： Brent Keeth , Pierre Fazan
发明人： Brent Keeth , Pierre Fazan
IPC分类号： H01L29/94
CPC分类号： H01L27/10888 , H01L27/105 , H01L27/108 , H01L27/10811
摘要： Processes are disclosed which facilitate improved high-density memory circuitry, most preferably dynamic random access memory (DRAM) circuitry. A semiconductor memory device includes i) a total of no more than 68,000,000 functional and operably addressable memory cells arranged in multiple memory arrays formed on a semiconductor die; and ii) circuitry formed on the semiconductor die permitting data to be written to and read from one or more of the memory cells. At least one of the memory arrays contains at least 100-square microns of continuous die surface area having at least 128 of the functional and operably addressable memory cells. More preferably, at least 100 square microns of continuous die surface area have at least 170 of the functional and operably addressable memory cells.
摘要翻译：公开了促进改进的高密度存储器电路，最优选动态随机存取存储器（DRAM）电路的方法。半导体存储器件包括i）总共不超过68,000,000个功能和可操作地寻址的存储器单元，布置在形成在半导体管芯上的多个存储器阵列中; 以及ii）形成在所述半导体管芯上的电路，允许将数据写入到所述存储器单元中的一个或多个存储单元并从其读取。存储器阵列中的至少一个包含至少100平方微米的具有至少128个功能和可操作寻址的存储器单元的连续管芯表面区域。更优选地，至少100平方微米的连续管芯表面区域具有至少170个功能和可操作寻址的存储器单元。

6. 发明授权

US07736959B2 Integrated circuit device, and method of fabricating same 有权
标题翻译：集成电路器件及其制造方法
公开(公告)号：US07736959B2
公开(公告)日：2010-06-15
申请号：US12069704
申请日：2008-02-12
申请人： Pierre Fazan
发明人： Pierre Fazan
IPC分类号： H01L21/8242
CPC分类号： H01L27/10894 , H01L21/845 , H01L27/105 , H01L27/1052 , H01L27/108 , H01L27/10802 , H01L27/10823 , H01L27/10826 , H01L27/10844 , H01L27/10897 , H01L27/1211 , H01L29/7841 , H01L29/785
摘要： There are many inventions described and illustrated herein. In a first aspect, the present invention is directed to integrated circuit device including SOI logic transistors and SOI memory transistors, and method for fabricating such a device. In one embodiment, integrated circuit device includes memory portion having, for example, PD or FD SOI memory cells, and logic portion having, for example, high performance transistors, such as Fin-FET, multiple gate transistors, and/or non-high performance transistors (such as single gate transistors that do not possess the performance characteristics of the high performance transistors). In another aspect, the present invention is directed to a method of manufacture of such integrated circuit device.
摘要翻译：这里描述和说明了许多发明。在第一方面，本发明涉及包括SOI逻辑晶体管和SOI存储晶体管的集成电路器件及其制造方法。在一个实施例中，集成电路器件包括具有例如PD或FD SOI存储器单元的存储器部分和具有例如诸如Fin-FET，多个栅极晶体管和/或非高电压的高性能晶体管的逻辑部分性能晶体管（例如不具有高性能晶体管的性能特性的单栅极晶体管）。另一方面，本发明涉及这种集成电路装置的制造方法。

7. 发明申请

US20080237714A1 Manufacturing Process for Zero-Capacitor Random Access Memory Circuits 有权
标题翻译：零电容随机存取存储器电路的制造工艺
公开(公告)号：US20080237714A1
公开(公告)日：2008-10-02
申请号：US12053398
申请日：2008-03-21
申请人： Pierre Fazan
发明人： Pierre Fazan
IPC分类号： H01L27/12 , H01L21/84 , C23F1/00
CPC分类号： H01L27/10805 , H01L21/84 , H01L27/108 , H01L27/10844 , H01L27/10847 , H01L27/1203 , H01L29/7841
摘要： Embodiments of a manufacturing process flow for producing standalone memory devices that can achieve bit cell sizes on the order of 4F2 or 5F2, and that can be applied to common source/drain, separate source/drain, or common source only or common drain only transistor arrays. Active area and word line patterns are formed as perpendicularly-arranged straight lines on a Silicon-on-Insulator substrate. The intersections of the active area and spaces between word lines define contact areas for the connection of vias and metal line layers. Insulative spacers are used to provide an etch mask pattern that allows the selective etching of contact areas as a series of linear trenches, thus facilitating straight line lithography techniques. Embodiments of the manufacturing process remove first layer metal (metal-1) islands and form elongated vias, in a succession of processing steps to build dense memory arrays.
摘要翻译：用于制造独立存储器件的制造工艺流程的实施例，其可以实现4F2或5F2的数量级的位单元尺寸，并且可以应用于公共源极/漏极，单独的源极/漏极或仅公共源极或仅公共漏极晶体管阵列有源区域和字线图案在绝缘体上硅衬底上形成为垂直布置的直线。活动区域和字线间的交点定义用于连接通孔和金属线层的接触区域。使用绝缘间隔物来提供蚀刻掩模图案，其允许将接触区域选择性地蚀刻为一系列线性沟槽，从而便于直线光刻技术。制造过程的实施例在连续的处理步骤中去除第一层金属（金属-1）岛并形成细长的通孔以构建密集的存储器阵列。

8. 发明申请

US20080153213A1 Integrated circuit device, and method of fabricating same 有权
标题翻译：集成电路器件及其制造方法
公开(公告)号：US20080153213A1
公开(公告)日：2008-06-26
申请号：US12069704
申请日：2008-02-12
申请人： Pierre Fazan
发明人： Pierre Fazan
IPC分类号： H01L21/782
CPC分类号： H01L27/10894 , H01L21/845 , H01L27/105 , H01L27/1052 , H01L27/108 , H01L27/10802 , H01L27/10823 , H01L27/10826 , H01L27/10844 , H01L27/10897 , H01L27/1211 , H01L29/7841 , H01L29/785
摘要： There are many inventions described and illustrated herein. In a first aspect, the present invention is directed to integrated circuit device including SOI logic transistors and SOI memory transistors, and method for fabricating such a device. In one embodiment, integrated circuit device includes memory portion having, for example, PD or FD SOI memory cells, and logic portion having, for example, high performance transistors, such as Fin-FET, multiple gate transistors, and/or non-high performance transistors (such as single gate transistors that do not possess the performance characteristics of the high performance transistors). In another aspect, the present invention is directed to a method of manufacture of such integrated circuit device.
摘要翻译：这里描述和说明了许多发明。在第一方面，本发明涉及包括SOI逻辑晶体管和SOI存储晶体管的集成电路器件及其制造方法。在一个实施例中，集成电路器件包括具有例如PD或FD SOI存储器单元的存储器部分，以及具有例如诸如Fin-FET，多个栅极晶体管和/或非高电位的高性能晶体管的逻辑部分性能晶体管（例如不具有高性能晶体管的性能特性的单栅极晶体管）。另一方面，本发明涉及这种集成电路装置的制造方法。

9. 发明授权

US07177175B2 Low power programming technique for a floating body memory transistor, memory cell, and memory array 有权
公开(公告)号：US07177175B2
公开(公告)日：2007-02-13
申请号：US11334338
申请日：2006-01-17
申请人： Pierre Fazan , Serguei Okhonin
发明人： Pierre Fazan , Serguei Okhonin
IPC分类号： G11C11/24 , H01L27/01
CPC分类号： G11C11/404 , G11C2211/4016 , H01L27/108 , H01L27/10802 , H01L29/7841
摘要： There are many inventions described and illustrated herein. In one aspect, the present invention is directed to a memory cell, architecture, and/or array and/or technique of writing or programming data into the memory cell (for example, a technique to write or program a logic low or State “0” in a memory cell employing an electrically floating body transistor. In this regard, the present invention programs a logic low or State “0” in the memory cell while the electrically floating body transistor is in the “OFF” state or substantially “OFF” state (for example, when the device has no (or practically no) channel and/or channel current between the source and drain). In this way, the memory cell may be programmed whereby there is little to no current/power consumption by the electrically floating body transistor and/or from memory array having a plurality of electrically floating body transistors.

10. 发明授权

US06936549B2 Chemical vapor deposition using organometallic precursors 失效
标题翻译：使用有机金属前体的化学气相沉积
公开(公告)号：US06936549B2
公开(公告)日：2005-08-30
申请号：US10737500
申请日：2003-12-16
申请人： Gurtej S. Sandhu , Pierre Fazan
发明人： Gurtej S. Sandhu , Pierre Fazan
IPC分类号： C23C16/40 , H01L21/316 , H01L21/8242 , H01L21/31 , H01L21/469
CPC分类号： H01L21/31604 , C23C16/40 , H01L27/10852
摘要： A multi-component layer is deposited on a semiconductor substrate in a semiconductor process. The multi-component layer may be a dielectric layer formed from a gaseous titanium organometallic precursor, reactive silane-based gas and a gaseous oxidant. The multi-component layer may be deposited in a cold wall or hot wall chemical vapor deposition (CVD) reactor, and in the presence or absence of plasma. The multi-component layer may also be deposited using other processes, such as radiant energy or rapid thermal CVD.
摘要翻译：在半导体工艺中在半导体衬底上沉积多组分层。多组分层可以是由气态钛有机金属前体，反应性硅烷基气体和气态氧化剂形成的电介质层。多组分层可以沉积在冷壁或热壁化学气相沉积（CVD）反应器中，并且在存在或不存在等离子体的情况下。多组分层也可以使用诸如辐射能或快速热CVD的其它过程进行沉积。

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