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1. 发明授权

US08806316B2 Circuits, integrated circuits, and methods for interleaved parity computation 有权
标题翻译：电路，集成电路和交错奇偶校验计算方法
公开(公告)号：US08806316B2
公开(公告)日：2014-08-12
申请号：US13348447
申请日：2012-01-11
申请人： Guorjuh Thomas Hwang , Chia Jen Chang
发明人： Guorjuh Thomas Hwang , Chia Jen Chang
IPC分类号： G06F11/00 , H03M13/00
CPC分类号： H03M13/2792 , G06F11/10 , G06F11/1048 , H03M13/098 , H03M13/6561
摘要： Circuits, integrated circuits, and methods are disclosed for interleaved parity computation. In one such example circuit, an interleaved parity computation circuit includes a first parity circuit that receives a first set of bits and a second parity circuit that receives a second set of bits. The first set of bits includes a first parity bit, and is received in the first parity circuit during a first clock cycle. The first parity circuit generates a first signal indicative of the parity of the first set of bits. The second set of bits includes a second parity bit, and is received in the second parity circuit during a second clock cycle. The second parity circuit generates a second signal indicative of the parity of the second set of bits. A combining circuit combines the first signal and the second signal into an alert signal.
摘要翻译：公开了用于交错奇偶校验计算的电路，集成电路和方法。在一个这样的示例电路中，交错奇偶校验计算电路包括接收第一组位的第一奇偶校验电路和接收第二组位的第二奇偶校验电路。第一组位包括第一奇偶校验位，并且在第一时钟周期期间在第一奇偶校验电路中接收。第一奇偶校验电路产生指示第一组位的奇偶性的第一信号。第二组位包括第二奇偶校验位，并且在第二时钟周期期间在第二奇偶校验电路中接收。第二奇偶校验电路产生指示第二组位的奇偶性的第二信号。组合电路将第一信号和第二信号组合成报警信号。

2. 发明申请

US20130179758A1 CIRCUITS, INTEGRATED CIRCUITS, AND METHODS FOR INTERLEAVED PARITY COMPUTATION 有权
标题翻译：电路，集成电路和交互式特征计算方法
公开(公告)号：US20130179758A1
公开(公告)日：2013-07-11
申请号：US13348447
申请日：2012-01-11
申请人： Guorjuh Thomas Hwang , Chia Jen Chang
发明人： Guorjuh Thomas Hwang , Chia Jen Chang
IPC分类号： H03M13/09 , G06F11/10
CPC分类号： H03M13/2792 , G06F11/10 , G06F11/1048 , H03M13/098 , H03M13/6561
摘要： Circuits, integrated circuits, and methods are disclosed for interleaved parity computation. In one such example circuit, an interleaved parity computation circuit includes a first parity circuit that receives a first set of bits and a second parity circuit that receives a second set of bits. The first set of bits includes a first parity bit, and is received in the first parity circuit during a first clock cycle. The first parity circuit generates a first signal indicative of the parity of the first set of bits. The second set of bits includes a second parity bit, and is received in the second parity circuit during a second clock cycle. The second parity circuit generates a second signal indicative of the parity of the second set of bits. A combining circuit combines the first signal and the second signal into an alert signal.
摘要翻译：公开了用于交错奇偶校验计算的电路，集成电路和方法。在一个这样的示例电路中，交错奇偶校验计算电路包括接收第一组位的第一奇偶校验电路和接收第二组位的第二奇偶校验电路。第一组位包括第一奇偶校验位，并且在第一时钟周期期间在第一奇偶校验电路中接收。第一奇偶校验电路产生指示第一组位的奇偶性的第一信号。第二组位包括第二奇偶校验位，并且在第二时钟周期期间在第二奇偶校验电路中接收。第二奇偶校验电路产生指示第二组位的奇偶性的第二信号。组合电路将第一信号和第二信号组合成报警信号。

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