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1. 发明授权

US08689202B1 Scheduling of instructions 有权
标题翻译：调度指令
公开(公告)号：US08689202B1
公开(公告)日：2014-04-01
申请号：US11096184
申请日：2005-03-30
申请人： Gunnar Braun , Andreas Hoffmann , Volker Grieve , Manuel Hohenauer , Rainer Leupers
发明人： Gunnar Braun , Andreas Hoffmann , Volker Grieve , Manuel Hohenauer , Rainer Leupers
IPC分类号： G06F9/45
CPC分类号： G06F8/445
摘要： A method of automatically extracting information from an architecture description. A memory resident directed acyclic graph data structure comprising nodes representing instructions and edges whose weights represent dependencies between pairs of instructions is constructed. A list of ready nodes are maintained in the directed acyclic graph. A list of nodes not scheduled is maintained. And, it is determined whether the next instruction to be scheduled is to be taken from the list of ready nodes or from the list of nodes not yet scheduled.
摘要翻译：一种从架构描述中自动提取信息的方法。存储器驻留定向非循环图数据结构包括表示指令的节点和其权重表示指令对之间依赖性的边。在有向非循环图中保留了一个可用节点列表。维护未调度的节点列表。并且，确定下一个要调度的指令是从准备节点的列表还是从尚未调度的节点的列表中取出。

2. 发明授权

US09280326B1 Compiler retargeting based on instruction semantic models 有权
标题翻译：基于指令语义模型的编译器重定向
公开(公告)号：US09280326B1
公开(公告)日：2016-03-08
申请号：US11140353
申请日：2005-05-26
申请人： Gunnar Braun , Andreas Hoffmann , Volker Greive , Rainer Leupers , Jianjiang Ceng
发明人： Gunnar Braun , Andreas Hoffmann , Volker Greive , Rainer Leupers , Jianjiang Ceng
IPC分类号： G06F9/45 , G06F9/44
CPC分类号： G06F8/37
摘要： Generating a description of compiler code selector rules from an architecture description. A method comprises accessing a target architecture model written in an architecture description language (ADL) and extracting semantic information therefrom to generate a plurality of semantic statements. Rules that map from source code operations to semantic patterns are accessed. The semantic statements are searched for matches for the semantic patterns to generate mappings that serve as a description of compiler code selector rules.
摘要翻译：从架构描述生成编译器代码选择器规则的描述。一种方法包括访问以架构描述语言（ADL）编写的目标体系结构模型，并从中提取语义信息以生成多个语义语句。访问从源代码操作映射到语义模式的规则。搜索语义语句用于语义模式的匹配，以生成用作编译器代码选择器规则的描述的映射。

3. 发明授权

US08086438B2 Method and system for instruction-set architecture simulation using just in time compilation 有权
标题翻译：使用即时编译的指令集架构仿真的方法和系统
公开(公告)号：US08086438B2
公开(公告)日：2011-12-27
申请号：US10309554
申请日：2002-12-03
申请人： Achim Nohl , Gunnar Braun , Andreas Hoffmann , Oliver Schliebusch , Rainer Leupers , Heinrich Myer
发明人： Achim Nohl , Gunnar Braun , Andreas Hoffmann , Oliver Schliebusch , Rainer Leupers , Heinrich Myer
IPC分类号： G06F9/44 , G06F9/455 , G06F9/26 , G06F9/30 , G06F7/38 , G06F9/45
CPC分类号： G06F9/45516 , G06F9/45504 , G06F17/5022
摘要： A method of simulating a program. Compiled and interpretive techniques are combined into a just-in-time cached compiled technique. When an instruction of a program simulation is to be executed at run-time, a table of compiled instructions is accessed to determine whether compiled data for the instruction is stored in the table. If the compiled data is not therein, the instruction is compiled and stored in the table. The compiled data is returned to a simulator that is executing the program simulation. In another embodiment, before storing new information in the table, another table may be consulted to determine if the location to which the new information is to be stored is protected. If the table location is protected, the new information is not stored in the table. Rather, the new information is simply passed on to the simulator.
摘要翻译：一种模拟程序的方法。编译和解释技术被组合成即时缓存编译技术。当在运行时执行程序仿真的指令时，访问编译指令的表以确定指令的编译数据是否存储在表中。如果编译数据不在其中，则该指令将被编译并存储在表中。将编译的数据返回到正在执行程序仿真的模拟器。在另一个实施例中，在将新信息存储在表中之前，可以参考另一个表来确定新信息要存储的位置是否被保护。如果表位置受到保护，新信息不会存储在表中。相反，新的信息只是传递给模拟器。

4. 发明授权

US07313773B1 Method and device for simulator generation based on semantic to behavioral translation 有权
标题翻译：基于语义到行为翻译的模拟器生成方法和装置
公开(公告)号：US07313773B1
公开(公告)日：2007-12-25
申请号：US11139373
申请日：2005-05-26
申请人： Gunnar Braun , Achim Nohl , Jianjiang Ceng , Andreas Hoffmann , Rainer Leupers
发明人： Gunnar Braun , Achim Nohl , Jianjiang Ceng , Andreas Hoffmann , Rainer Leupers
IPC分类号： G06F17/50 , G06F9/45 , G06F9/455
CPC分类号： G06F17/5022
摘要： Generating a simulator from an architecture description. A target architecture model described in an architecture description language (ADL) is accessed. The model comprises a semantic representation of an instruction set for the target architecture. The semantic representation is translated to a behavioral representation. The simulator is automatically generated from the behavioral representation. A compiler may also be generated from the semantic representation.
摘要翻译：从架构描述生成模拟器。访问架构描述语言（ADL）中描述的目标体系结构模型。该模型包括用于目标架构的指令集的语义表示。语义表示被转换为行为表示。模拟器是从行为表示自动生成的。也可以从语义表示中生成编译器。

5. 发明授权

US08554535B2 Instruction-set architecture simulation techniques using just in time compilation 有权
标题翻译：指令集架构仿真技术使用即时编译
公开(公告)号：US08554535B2
公开(公告)日：2013-10-08
申请号：US13338155
申请日：2011-12-27
申请人： Achim Nohl , Gunnar Braun , Andreas Hoffmann , Oliver Schliebusch , Rainer Leupers , Heinrich Myer
发明人： Achim Nohl , Gunnar Braun , Andreas Hoffmann , Oliver Schliebusch , Rainer Leupers , Heinrich Myer
IPC分类号： G06F9/455
CPC分类号： G06F9/45516 , G06F9/45504 , G06F17/5022
摘要： A method of simulating a program. Compiled and interpretive techniques are combined into a just-in-time cached compiled technique. When an instruction of a program simulation is to be executed at run-time, a table of compiled instructions is accessed to determine whether compiled data for the instruction is stored in the table. If the compiled data is not therein, the instruction is compiled and stored in the table. The compiled data is returned to a simulator that is executing the program simulation. In another embodiment, before storing new information in the table, another table may be consulted to determine if the location to which the new information is to be stored is protected. If the table location is protected, the new information is not stored in the table. Rather, the new information is simply passed on to the simulator.
摘要翻译：一种模拟程序的方法。编译和解释技术被组合成即时缓存编译技术。当在运行时执行程序仿真的指令时，访问编译指令的表以确定指令的编译数据是否存储在表中。如果编译数据不在其中，则该指令将被编译并存储在表中。将编译的数据返回到正在执行程序仿真的模拟器。在另一个实施例中，在将新信息存储在表中之前，可以参考另一个表来确定新信息要存储的位置是否被保护。如果表位置受到保护，新信息不会存储在表中。相反，新的信息只是传递给模拟器。

6. 发明申请

US20120158397A1 INSTRUCTION-SET ARCHITECTURE SIMULATION TECHNIQUES USING JUST IN TIME COMPILATION 有权
标题翻译：指导性建筑模拟技术在时间编译中使用
公开(公告)号：US20120158397A1
公开(公告)日：2012-06-21
申请号：US13338155
申请日：2011-12-27
申请人： Achim Nohl , Gunnar Braun , Andreas Hoffmann , Oliver Schliebusch , Rainer Leupers , Heinrich Myer
发明人： Achim Nohl , Gunnar Braun , Andreas Hoffmann , Oliver Schliebusch , Rainer Leupers , Heinrich Myer
IPC分类号： G06F9/44 , G06F9/45 , G06F9/30 , G06F9/455 , G06F9/26
CPC分类号： G06F9/45516 , G06F9/45504 , G06F17/5022
摘要： A method of simulating a program. Compiled and interpretive techniques are combined into a just-in-time cached compiled technique. When an instruction of a program simulation is to be executed at run-time, a table of compiled instructions is accessed to determine whether compiled data for the instruction is stored in the table. If the compiled data is not therein, the instruction is compiled and stored in the table. The compiled data is returned to a simulator that is executing the program simulation. In another embodiment, before storing new information in the table, another table may be consulted to determine if the location to which the new information is to be stored is protected. If the table location is protected, the new information is not stored in the table. Rather, the new information is simply passed on to the simulator.
摘要翻译：一种模拟程序的方法。编译和解释技术被组合成即时缓存编译技术。当在运行时执行程序仿真的指令时，访问编译指令的表以确定指令的编译数据是否存储在表中。如果编译数据不在其中，则该指令将被编译并存储在表中。将编译的数据返回到正在执行程序仿真的模拟器。在另一个实施例中，在将新信息存储在表中之前，可以参考另一个表来确定新信息要存储的位置是否被保护。如果表位置受到保护，新信息不会存储在表中。相反，新的信息只是传递给模拟器。

7. 发明授权

US09064076B1 User interface for facilitation of high level generation of processor extensions 有权
标题翻译：用于高级别处理器扩展的便利化界面
公开(公告)号：US09064076B1
公开(公告)日：2015-06-23
申请号：US11388484
申请日：2006-03-23
申请人： Gunnar Braun , Frank Fiedler , Andreas Hoffmann , Gideon Intrater , Olaf Lüthje , Achim Nohl , Ludwig Rieder
发明人： Gunnar Braun , Frank Fiedler , Andreas Hoffmann , Gideon Intrater , Olaf Lüthje , Achim Nohl , Ludwig Rieder
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5045 , G06F2217/68
摘要： Systems and methods of user interface for facilitation of high level generation of processor extensions. In accordance with a method embodiment of the present invention, an instruction format is accessed at a graphical user interface. A programming language description of a computation element for an execution unit of the processor extension is accessed. A representation of a hardware design for the processor extension comprising the instruction format and the computation element is generated.
摘要翻译：用于提升高级处理器扩展的用户界面的系统和方法。根据本发明的方法实施例，在图形用户界面处访问指令格式。访问用于处理器扩展的执行单元的计算元件的编程语言描述。生成包括指令格式和计算元素的处理器扩展的硬件设计的表示。

8. 发明授权

US07788078B1 Processor/memory co-exploration at multiple abstraction levels 有权
标题翻译：处理器/内存在多个抽象级别的共同探索
公开(公告)号：US07788078B1
公开(公告)日：2010-08-31
申请号：US11069496
申请日：2005-02-28
申请人： Gunnar Braun , Olaf Zorres , Achim Nohl , Andreas Hoffmann
发明人： Gunnar Braun , Olaf Zorres , Achim Nohl , Andreas Hoffmann
IPC分类号： G06F17/50 , G01R31/28
CPC分类号： G06F17/5022 , G06F2217/86
摘要： Processor/memory co-exploration at multiple abstraction levels. An architecture description language (ADL) description of a processor/memory system is accessed. The ADL description models on one of a plurality of abstraction levels. The abstraction levels may include a functional (or bit-accurate) level and a cycle-accurate level. Further, a communication protocol for the processor/memory system is accessed. The communication protocol is formed from primitives, wherein a memory interface formed from the primitives is useable in simulation at the abstraction levels. A processor/memory simulation model is automatically generated from the description and description of the communication protocol. The processor/memory simulation model comprises a processor/memory interface comprising the primitives and based on the communication protocol. The memory interface allows simulation of the processor/memory on the appropriate abstraction level for the simulation. For example, the processor/memory interface may be a functional interface or a cycle-accurate interface.
摘要翻译：处理器/内存在多个抽象级别的共同探索。访问处理器/存储器系统的架构描述语言（ADL）描述。 ADL描述模型在多个抽象级别之一上。抽象级别可以包括功能（或比特精确）级别和循环准确级别。此外，访问用于处理器/存储器系统的通信协议。通信协议由原语形成，其中由原语形成的存储器接口可在抽象级别的仿真中使用。从通信协议的描述和描述中自动生成处理器/存储器模拟模型。处理器/存储器模拟模型包括包括原语并基于通信协议的处理器/存储器接口。存储器接口允许在适当的抽象级别上仿真处理器/存储器进行仿真。例如，处理器/存储器接口可以是功能接口或周期准确的接口。

9. 发明申请

US20100324880A1 Techniques for Processor/Memory Co-Exploration at Multiple Abstraction Levels 有权
标题翻译：多抽象层处理器/内存共同探索技术
公开(公告)号：US20100324880A1
公开(公告)日：2010-12-23
申请号：US12871884
申请日：2010-08-30
申请人： Gunnar Braun , Olaf Zorres , Achim Nohl , Andreas Hoffmann
发明人： Gunnar Braun , Olaf Zorres , Achim Nohl , Andreas Hoffmann
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F2217/86
摘要： Processor/memory co-exploration at multiple abstraction levels. An architecture description language (ADL) description of a processor/memory system is accessed. The ADL description models on one of a plurality of abstraction levels. The abstraction levels may include a functional (or bit-accurate) level and a cycle-accurate level. Further, a communication protocol for the processor/memory system is accessed. The communication protocol is formed from primitives, wherein a memory interface formed from the primitives is useable in simulation at the abstraction levels. A processor/memory simulation model is automatically generated from the description and description of the communication protocol. The processor/memory simulation model comprises a processor/memory interface comprising the primitives and based on the communication protocol. The memory interface allows simulation of the processor/memory on the appropriate abstraction level for the simulation. For example, the processor/memory interface may be a functional interface or a cycle-accurate interface.
摘要翻译：处理器/内存在多个抽象级别的共同探索。访问处理器/存储器系统的架构描述语言（ADL）描述。 ADL描述模型在多个抽象级别之一上。抽象级别可以包括功能（或比特精确）级别和循环准确级别。此外，访问用于处理器/存储器系统的通信协议。通信协议由原语形成，其中由原语形成的存储器接口可在抽象级别的仿真中使用。从通信协议的描述和描述中自动生成处理器/存储器模拟模型。处理器/存储器模拟模型包括包括原语并基于通信协议的处理器/存储器接口。存储器接口允许在适当的抽象级别上仿真处理器/存储器进行仿真。例如，处理器/存储器接口可以是功能接口或周期准确的接口。

10. 发明授权

US08706453B2 Techniques for processor/memory co-exploration at multiple abstraction levels 有权
标题翻译：处理器/存储器在多个抽象级别共同探索的技术
公开(公告)号：US08706453B2
公开(公告)日：2014-04-22
申请号：US13648251
申请日：2012-10-09
申请人： Gunnar Braun , Olaf W. J. Zerres , Achim Nohl , Andreas Hoffmann
发明人： Gunnar Braun , Olaf W. J. Zerres , Achim Nohl , Andreas Hoffmann
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F2217/86
摘要： Processor/memory co-exploration at multiple abstraction levels. An architecture description language (ADL) description of a processor/memory system is accessed. The ADL description models on one of a plurality of abstraction levels. The abstraction levels may include a functional (or bit-accurate) level and a cycle-accurate level. Further, a communication protocol for the processor/memory system is accessed. The communication protocol is formed from primitives, wherein a memory interface formed from the primitives is useable in simulation at the abstraction levels. A processor/memory simulation model is automatically generated from the description and description of the communication protocol. The processor/memory simulation model comprises a processor/memory interface comprising the primitives and based on the communication protocol. The memory interface allows simulation of the processor/memory on the appropriate abstraction level for the simulation. For example, the processor/memory interface may be a functional interface or a cycle-accurate interface.
摘要翻译：处理器/内存在多个抽象级别的共同探索。访问处理器/存储器系统的架构描述语言（ADL）描述。 ADL描述模型在多个抽象级别之一上。抽象级别可以包括功能（或比特精确）级别和循环准确级别。此外，访问用于处理器/存储器系统的通信协议。通信协议由原语形成，其中由原语形成的存储器接口可在抽象级别的仿真中使用。从通信协议的描述和描述中自动生成处理器/存储器模拟模型。处理器/存储器模拟模型包括包括原语并基于通信协议的处理器/存储器接口。存储器接口允许在适当的抽象级别上仿真处理器/存储器进行仿真。例如，处理器/存储器接口可以是功能接口或周期准确的接口。

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