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1. 发明授权

US09875105B2 Checkpointed buffer for re-entry from runahead 有权
公开(公告)号：US09875105B2
公开(公告)日：2018-01-23
申请号：US13463627
申请日：2012-05-03
申请人： Guillermo J. Rozas , Paul Serris , Brad Hoyt , Sridharan Ramakrishnan , Hens Vanderschoot , Ross Segelken , Darrell Boggs , Magnus Ekman
发明人： Guillermo J. Rozas , Paul Serris , Brad Hoyt , Sridharan Ramakrishnan , Hens Vanderschoot , Ross Segelken , Darrell Boggs , Magnus Ekman
IPC分类号： G06F9/38
CPC分类号： G06F9/3802 , G06F9/3814 , G06F9/3863
摘要： Embodiments related to re-dispatching an instruction selected for re-execution from a buffer upon a microprocessor re-entering a particular execution location after runahead are provided. In one example, a microprocessor is provided. The example microprocessor includes fetch logic, one or more execution mechanisms for executing a retrieved instruction provided by the fetch logic, and scheduler logic for scheduling the retrieved instruction for execution. The example scheduler logic includes a buffer for storing the retrieved instruction and one or more additional instructions, the scheduler logic being configured, upon the microprocessor re-entering at a particular execution location after runahead, to re-dispatch, from the buffer, an instruction that has been previously dispatched to one of the execution mechanisms.

2. 发明申请

US20130297911A1 CHECKPOINTED BUFFER FOR RE-ENTRY FROM RUNAHEAD 有权
标题翻译：从RUNAHEAD重新进入的检查缓冲区
公开(公告)号：US20130297911A1
公开(公告)日：2013-11-07
申请号：US13463627
申请日：2012-05-03
申请人： Guillermo J. Rozas , Paul Serris , Brad Hoyt , Sridharan Ramakrishnan , Hens Vanderschoot , Ross Segelken , Darrell Boggs , Magnus Ekman
发明人： Guillermo J. Rozas , Paul Serris , Brad Hoyt , Sridharan Ramakrishnan , Hens Vanderschoot , Ross Segelken , Darrell Boggs , Magnus Ekman
IPC分类号： G06F9/30
CPC分类号： G06F9/3802 , G06F9/3814 , G06F9/3863
摘要： Embodiments related to re-dispatching an instruction selected for re-execution from a buffer upon a microprocessor re-entering a particular execution location after runahead are provided. In one example, a microprocessor is provided. The example microprocessor includes fetch logic, one or more execution mechanisms for executing a retrieved instruction provided by the fetch logic, and scheduler logic for scheduling the retrieved instruction for execution. The example scheduler logic includes a buffer for storing the retrieved instruction and one or more additional instructions, the scheduler logic being configured, upon the microprocessor re-entering at a particular execution location after runahead, to re-dispatch, from the buffer, an instruction that has been previously dispatched to one of the execution mechanisms.
摘要翻译：在提供微控制器重新进入特定执行位置之后，重新分派从缓冲器重新执行的指令的实施例。在一个示例中，提供微处理器。示例微处理器包括提取逻辑，用于执行由提取逻辑提供的检索指令的一个或多个执行机制，以及用于调度所检索的指令以执行的调度器逻辑。示例调度器逻辑包括用于存储检索到的指令和一个或多个附加指令的缓冲器，调度器逻辑被配置为在微控制器在经过前导头之后的特定执行位置重新进入时从缓冲器重新发送指令以前已经分配到其中一个执行机制。

3. 发明授权

US06842837B1 Method and apparatus for a burst write in a shared bus architecture 有权
标题翻译：在共享总线架构中用于突发写入的方法和装置
公开(公告)号：US06842837B1
公开(公告)日：2005-01-11
申请号：US09784274
申请日：2001-02-13
申请人： Mark Peting , Hens Vanderschoot
发明人： Mark Peting , Hens Vanderschoot
IPC分类号： G06F12/00 , G06F13/16
CPC分类号： G06F13/161
摘要： A method and apparatus for a burst mode write in a shared bus architecture comprising detecting a write data burst, determining if at least one memory unit is available to receive the write data burst, writing the write data burst to the at least one memory unit if the at least one memory unit is available to receive data. Storing a first portion of the write data burst in a buffer, concurrently with activating the at least one memory unit to receive data, if the at least one memory unit is not available to receive data; writing a second portion of the write data burst to the at least one memory unit when the at least one memory unit is available to receive data, and writing the first portion of the write data burst from the buffer to the at least one memory unit after writing the second portion of the write data burst.
摘要翻译：一种用于在共享总线架构中的突发模式写入的方法和装置，包括检测写入数据脉冲串，确定至少一个存储器单元是否可用于接收写入数据脉冲串，将写入数据脉冲串写入至少一个存储器单元，如果所述至少一个存储器单元可用于接收数据。如果所述至少一个存储器单元不可用于接收数据，则将写入数据突发的第一部分存储在缓冲器中，同时激活所述至少一个存储器单元以接收数据; 当所述至少一个存储器单元可用于接收数据时，将所述写入数据脉冲串的第二部分写入所述至少一个存储器单元，以及将所述写入数据脉冲串的所述第一部分从所述缓冲器写入所述至少一个存储器单元。写入写入数据突发的第二部分。

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