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    • 8. 发明申请
    • Processor for Executing an Aes-Type Algorithm
    • 用于执行Aes类型算法的处理器
    • US20080285745A1
    • 2008-11-20
    • US11547195
    • 2004-03-29
    • Yannick TegliaFabrice RomainPierre-Yvan LiardetPasqualina FragnetoFabio SozzaniGuido Bertoni
    • Yannick TegliaFabrice RomainPierre-Yvan LiardetPasqualina FragnetoFabio SozzaniGuido Bertoni
    • H04L9/06
    • H04L9/0631H04L9/003H04L2209/046H04L2209/08H04L2209/122
    • A processor for executing a Rijndeal algorithm which applies a plurality of encryption rounds to a data block array in order to obtain an array of identical size, each round involving a key block array and a data block substitution table, wherein said processor comprises: a first input register (102) containing an input data block column; an output register (111) containing an output data block column or an intermediate block column; a second input register (101) containing a key block column or the intermediate data blocks; a block substitution element (104) receiving the data one block at a time following the selection (103) thereof in the first register and providing, for each block, a column of blocks; an element (109) applying a cyclic permutation to the substitution circuit column blocks; and an Exclusive-OR combination element (110) combining the permutation circuit column blocks with the content of the second register, the result of said combination being loaded into the output register.
    • 一种用于执行Rijndeal算法的处理器,该Rijndeal算法将多个加密回合应用于数据块阵列,以便获得相同大小的阵列,每轮涉及密钥块阵列和数据块替换表,其中所述处理器包括:第一 输入寄存器(102),其包含输入数据块列; 包含输出数据块列或中间块列的输出寄存器(111); 包含密钥块列或中间数据块的第二输入寄存器(101); 块替换元件(104)在第一寄存器中的选择(103)之后的时间接收数据一个块,并为每个块提供一列块; 向替代电路列块施加循环置换的元件(109); 以及将置换电路列块与第二寄存器的内容组合的异或组合元件(110),所述组合的结果被加载到输出寄存器中。
    • 9. 发明授权
    • Circuit for the inner or scalar product computation in Galois fields
    • 伽罗瓦域内部或标量积计算电路
    • US07206410B2
    • 2007-04-17
    • US09974176
    • 2001-10-10
    • Guido BertoniLuca BreveglieriPasqualina Fragneto
    • Guido BertoniLuca BreveglieriPasqualina Fragneto
    • G06F7/00
    • G06F7/724
    • A circuit for computing the inner of scalar product of two vectors in a finite Galois field defined by a generator polynomial, wherein each vector includes at least two elements belonging to said finite field, comprises one or more look-up tables storing digital words indicative of said possible combinations and said possible reductions. The digital words in question are defined as a function of the second elements of said vectors and the generator polynomial of the field. The input register(s) and the look-up table(s) are configured to co-operate in a plurality of subsequent steps to generate at each step a partial product result identified by at least one of digital word addressed in a corresponding look-up table as a function of the digital signals stored in the input register(s). The circuit also includes an accumulator unit for adding up the partial results generated at each step to give a final product result deriving from accumulation of said partial results.
    • 一种用于计算由生成多项式定义的有限伽罗瓦域中的两个向量的标量积的内部的电路,其中每个向量包括属于所述有限域的至少两个元素,包括一个或多个查找表,其存储指示 说可能的组合和所述可能的减少。 所讨论的数字词被定义为所述向量的第二元素和场的生成多项式的函数。 输入寄存器和查找表被配置为在多个后续步骤中协作以在每个步骤处生成由相应查找表中寻址的数字字中的至少一个标识的部分乘积结果, 作为存储在输入寄存器中的数字信号的函数。 该电路还包括用于将在每个步骤产生的部分结果相加以产生从所述部分结果的积累得到的最终产品结果的累加器单元。