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1. 发明授权

US08082532B1 Placing complex function blocks on a programmable integrated circuit 有权
标题翻译：将复杂功能块放在可编程集成电路上
公开(公告)号：US08082532B1
公开(公告)日：2011-12-20
申请号：US12364719
申请日：2009-02-03
申请人： Guenter Stenz , Rajat Aggarwal
发明人： Guenter Stenz , Rajat Aggarwal
IPC分类号： G06F17/50
CPC分类号： G06F17/5054 , G06F17/5072
摘要： A computer-implemented method of implementing a circuit design within an integrated circuit (IC) can include, within an undirected graph representing the circuit design comprising nodes and edges, wherein each node represents a complex function block (CFB) or a pre-placed component of the circuit design and each edge represents at least one connection linking a pair of CFBs of the circuit design, determining an edge weight for each edge. The CFBs can be initially placed and a distance between each pair of CFBs joined by an edge of the undirected graph can be calculated. The CFB placement can be annealed by minimizing a cost function that calculates, for each edge, a product of the edge weight and the distance between the pair of CFBs joined by the edge. The cost function also can sum the products for each edge. The CFB placement can be stored.
摘要翻译：在集成电路（IC）内实现电路设计的计算机实现的方法可以包括在表示包括节点和边缘的电路设计的无向图中，其中每个节点表示复合功能块（CFB）或预置组件的电路设计，每个边缘表示连接电路设计的一对CFB的至少一个连接，确定每个边缘的边缘权重。可以首先放置CFB，并且可以计算通过无向图的边缘连接的每对CFB之间的距离。 CFB放置可以通过最小化成本函数进行退火，该成本函数为每个边缘计算边缘权重的乘积和边缘连接的一对CFB之间的距离。成本函数也可以对每个边缘的产品求和。可以存储CFB位置。

2. 发明授权

US07149993B1 Method, system, and apparatus for incremental design in programmable logic devices using floorplanning 有权
标题翻译：使用布局规划的可编程逻辑器件中增量设计的方法，系统和装置
公开(公告)号：US07149993B1
公开(公告)日：2006-12-12
申请号：US10812550
申请日：2004-03-29
申请人： Rajat Aggarwal , Guenter Stenz , Srinivasan Dasasathyan
发明人： Rajat Aggarwal , Guenter Stenz , Srinivasan Dasasathyan
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A method of designing a programmable logic device can include receiving a modification to a programmable logic device that has been floorplanned. Modules of the programmable logic device that have been changed by the modification can be identified. The changed modules can be floorplanned thereby determining a placement solution that does not violate boundaries of unchanged modules. The programmable logic device then can be placed and routed.
摘要翻译：设计可编程逻辑器件的方法可以包括接收对已被计划设计的可编程逻辑器件的修改。可以识别通过修改而改变的可编程逻辑器件的模块。更改的模块可以进行布局，从而确定不违反未更改模块边界的布局解决方案。然后，可编程逻辑器件可以放置和布线。

3. 发明授权

US08312405B1 Method of placing input/output blocks on an integrated circuit device 有权
标题翻译：在集成电路设备上放置输入/输出块的方法
公开(公告)号：US08312405B1
公开(公告)日：2012-11-13
申请号：US12356349
申请日：2009-01-20
申请人： Victor Slonim , Rajat Aggarwal , Guenter Stenz , Srinivasan Dasasathyan
发明人： Victor Slonim , Rajat Aggarwal , Guenter Stenz , Srinivasan Dasasathyan
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A method of placing input/output blocks on an integrated circuit device is described. The method may comprise receiving a circuit design having a plurality of input/output blocks to be placed at input/output sites of the integrated circuit device; modifying, for each input/output block of the circuit design, an input/output standard for the input/output block to include bus information; assigning, for each input/output block of the circuit design, an input/output site for the input/output block; and generating an input/output placement for the input/output blocks of the circuit design. A computer product is also disclosed.
摘要翻译：描述了在集成电路装置上放置输入/输出块的方法。该方法可以包括接收具有多个输入/输出块以放置在集成电路器件的输入/输出位置处的电路设计; 修改对于电路设计的每个输入/输出块，输入/输出块的输入/输出标准包括总线信息; 为电路设计的每个输入/输出块分配用于输入/输出块的输入/输出站点; 以及为电路设计的输入/输出块生成输入/输出布局。还公开了一种计算机产品。

4. 发明授权

US07313778B1 Method system and apparatus for floorplanning programmable logic designs 有权
标题翻译：用于布局规划可编程逻辑设计的方法系统和装置
公开(公告)号：US07313778B1
公开(公告)日：2007-12-25
申请号：US10787326
申请日：2004-02-26
申请人： Guenter Stenz , Srinivasan Dasasathyan , Rajat Aggarwal , James L. Saunders
发明人： Guenter Stenz , Srinivasan Dasasathyan , Rajat Aggarwal , James L. Saunders
IPC分类号： G06F17/50
CPC分类号： G06F17/5054 , G06F17/5072
摘要： A method (600) of designing a programmable logic device can include the steps of identifying a cost function that penalizes floorplans of a circuit design that do not fit on the programmable logic device (605) and defining modules having components of a same type (615). A set of shapes associated with a module can be determined (610). The circuit design can be annealed (620) to determine a floorplan using the cost function and the set of shapes for the module.
摘要翻译：设计可编程逻辑器件的方法（600）可以包括以下步骤：识别损害不适合于可编程逻辑器件（605）并且限定具有相同类型的部件的模块（615）的电路设计的平面图的成本函数）。可以确定与模块相关联的一组形状（610）。电路设计可以退火（620），以使用成本函数和模块的形状集来确定平面图。

5. 发明授权

US08010924B1 Assignment of select input/output blocks to banks for integrated circuits using integer linear programming with proximity optimization 有权
标题翻译：使用具有邻近优化的整数线性规划将选择输入/输出块分配给集成电路组
公开(公告)号：US08010924B1
公开(公告)日：2011-08-30
申请号：US12184108
申请日：2008-07-31
申请人： Victor Z. Slonim , Parivallal Kannan , Guenter Stenz
发明人： Victor Z. Slonim , Parivallal Kannan , Guenter Stenz
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： A method of assigning a plurality of input/output (I/O) objects of a circuit design to banks of a programmable integrated circuit (IC) using integer linear programming can include storing a plurality of constraints that depend upon a plurality of variables, wherein the plurality of constraints regulate assignment of each of the plurality of I/O objects to banks of the programmable IC (125-184), and storing a linear function that depends upon the plurality of constraints and a plurality of cost metrics, wherein each cost metric imposes a penalty when a selected I/O object of the circuit design is assigned to a bank of the programmable IC that is different from a bank to which the selected I/O object is assigned within a reference solution that is infeasible (190). A result indicating whether a feasible solution exists for assignment of the plurality of I/O objects of the circuit design to banks of the target programmable IC can be determined by minimizing the linear function (192) subject to the plurality of constraints and outputting the result (196, 198).
摘要翻译：使用整数线性规划将电路设计的多个输入/输出（I / O）对象分配给可编程集成电路（IC）的组的方法可以包括存储取决于多个变量的多个约束，其中所述多个约束调节所述多个I / O对象中的每一个到所述可编程IC（125-184）的存储体的分配，以及存储取决于所述多个约束和多个成本度量的线性函数，其中每个成本当电路设计的所选择的I / O对象被分配给可编程IC的存储体时，在不可执行的参考解决方案中将所选择的I / O对象分配给不同于存储体的存储体（190）。可以通过使受限于多个约束的线性函数（192）最小化并输出结果来确定是否存在用于将电路设计的多个I / O对象分配给目标可编程IC的组的可行解的结果（196，198）。

6. 发明授权

US07072815B1 Relocation of components for post-placement optimization 有权
标题翻译：迁移后的优化组件
公开(公告)号：US07072815B1
公开(公告)日：2006-07-04
申请号：US10213775
申请日：2002-08-06
申请人： Kamal Chaudhary , Krishnan Anandh , Sudip K. Nag , Guenter Stenz
发明人： Kamal Chaudhary , Krishnan Anandh , Sudip K. Nag , Guenter Stenz
IPC分类号： G06F9/455
CPC分类号： G06F17/5072
摘要： Method and apparatus for post-placement optimization of resources for connections is described. To optimize resource placement, search windows are generated responsive to driver and load components, as well as to a connection between the driver and load components. Adding in a straight-line path search window may be used as an alternative where a bypassed resource is to be relocated. Using connection-based optimization in combination with driver- and resource-based optimization results in improved optimization with negligible impact on runtime.
摘要翻译：描述了用于连接资源的放置后优化的方法和装置。为了优化资源放置，响应于驱动程序和加载组件以及驱动程序和加载组件之间的连接生成搜索窗口。可以使用在直线路径搜索窗口中添加旁路资源被重新定位的替代方案。使用基于连接的优化与基于驱动程序和资源的优化结合可以改善优化，对运行时的影响可以忽略不计。

7. 发明授权

US07958480B1 Placement of I/O blocks within I/O banks using an integer linear programming formulation 有权
标题翻译：使用整数线性规划公式在I / O库中放置I / O块
公开(公告)号：US07958480B1
公开(公告)日：2011-06-07
申请号：US12106564
申请日：2008-04-21
申请人： Victor Z. Slonim , Parivallal Kannan , Guenter Stenz
发明人： Victor Z. Slonim , Parivallal Kannan , Guenter Stenz
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A method of input/output (I/O) block placement assigned to an input/output bank includes formulating a placement algorithm using integer linear programming (ILP) and simultaneously placing single groups and Relatively Placed Module (RPM) groups of I/O blocks in the I/O bank. The method further includes determining a placeability matrix P and a binary assignment matrix X used for the ILP. The method can further eliminate all assignment matrix elements of X equal to 0 in the integer linear programming and re-index any remaining elements. The method can further place all I/O blocks according to a solution if solving of the standard ILP formulation results in a feasible solution. Optionally, the method generates a placement solution that is as close as possible to an external reference solution specified by designer. Optionally, the method analyzes which constraints were violated and generates useful error information.
摘要翻译：分配给输入/输出组的输入/输出（I / O）块布局的方法包括使用整数线性规划（ILP）制定放置算法，同时放置单组和相对放置模块（RPM）组的I / O块在I / O银行。该方法还包括确定可用性矩阵P和用于ILP的二进制分配矩阵X. 该方法可以进一步消除整数线性规划中X等于0的所有分配矩阵元素，并重新索引任何剩余的元素。如果解决标准ILP公式导致可行的解决方案，则该方法可以根据解决方案进一步放置所有I / O块。可选地，该方法生成尽可能接近由设计者指定的外部参考解决方案的放置解决方案。可选地，该方法分析哪些约束被违反并且产生有用的错误信息。

8. 发明授权

US06957406B1 Analytical placement methods with minimum preplaced components 有权
标题翻译：具有最小预置部件的分析放置方法
公开(公告)号：US06957406B1
公开(公告)日：2005-10-18
申请号：US10273074
申请日：2002-10-16
申请人： Guenter Stenz
发明人： Guenter Stenz
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： The invention relates to a method for placing design components of an integrated circuit. A first site is selected. Other sites that are at maximum distances from already used sites may be selected. Components that have minimum connectivity to already placed components are selected. These components are used for preplacement. Preferably, the number of preplaced components is small. The rest of the design components are placed. An overlap ratio is computed. If the overlap ratio is above a predetermined value, the result is unplaced and additional components are preplaced. Another placement is performed. Overlap ratio is again computed. The steps of unplacing, adding preplaced components and computing overlap ratio are repeated until the overlap ratio falls below the predetermined value.
摘要翻译：本发明涉及一种用于放置集成电路的设计组件的方法。选择了第一个网站。可以选择距离已经使用的站点最远的其他站点。选择与已放置组件具有最小连接性的组件。这些组件用于预放置。优选地，预置部件的数量很小。其余的设计组件被放置。计算重叠率。如果重叠率高于预定值，则结果是未放置的并且预先设置附加组件。执行另一个放置。再次计算重叠比。重复放置步骤，添加预放置组件和计算重叠率，直到重叠率低于预定值。

9. 发明授权

US06857115B1 Placement of objects with partial shape restriction 有权
标题翻译：放置具有局部形状限制的物体
公开(公告)号：US06857115B1
公开(公告)日：2005-02-15
申请号：US10215602
申请日：2002-08-08
申请人： Srinivasan Dasasathyan , Guenter Stenz , Sudip K. Nag , Jason H. Anderson
发明人： Srinivasan Dasasathyan , Guenter Stenz , Sudip K. Nag , Jason H. Anderson
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： Application of network flow techniques to constrained optimization problems is disclosed. The present of constrains may lead to infeasible solutions. The infeasible solutions can be removed by an iterative process of changing the structure of the network and/or the associated parameters. Specific applications of the invention to the placement of tristate buffers and clocks in integrated circuits are disclosed.
摘要翻译：公开了网络流技术对约束优化问题的应用。约束的存在可能导致不可行的解决方案。可以通过改变网络结构和/或相关参数的迭代过程来消除不可行的解决方案。公开了本发明在集成电路中放置三态缓冲器和时钟的具体应用。

10. 发明授权

US07512922B1 Methods of structured placement of a circuit design 有权
标题翻译：电路设计的结构化放置方法
公开(公告)号：US07512922B1
公开(公告)日：2009-03-31
申请号：US11787812
申请日：2007-04-18
申请人： Guenter Stenz
发明人： Guenter Stenz
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F2217/84
摘要： A method of creating relatively placed macros (RPMS) for a circuit design for a target device can include determining N best configurations for each of a plurality of connections of the circuit design, wherein each configuration specifies relative positioning of a source and a load of a connection and an estimated delay for the connection. The method can include calculating a maximum allowable delay for each of the plurality of connections of the circuit design and determining that a connection selected from the plurality of connections is critical according to the N best configurations associated with the critical connection and the maximum delay of the critical connection. A configuration from the N best configurations associated with the critical connection can be selected. An RPM for the critical connection can be generated using the selected configuration.
摘要翻译：为目标设备的电路设计创建相对放置的宏（RPMS）的方法可以包括为电路设计的多个连接中的每一个确定N个最佳配置，其中每个配置规定源和负载的相对定位连接和估计的连接延迟。该方法可以包括计算电路设计的多个连接中的每一个的最大可允许延迟，并且根据与关键连接相关的N个最佳配置和最大延迟时间确定从多个连接中选择的连接是关键的关键连接。可以选择与关键连接相关的N个最佳配置的配置。可以使用所选配置生成关键连接的RPM。

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