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1. 发明申请

US20050200390A1 Highly configurable PLL architecture for programmable logic 有权
标题翻译：用于可编程逻辑的高度可配置的PLL架构
公开(公告)号：US20050200390A1
公开(公告)日：2005-09-15
申请号：US10797836
申请日：2004-03-09
申请人： Gregory Starr , Wanli Chang , Kang Lai , Mian Smith , Richard Chang
发明人： Gregory Starr , Wanli Chang , Kang Lai , Mian Smith , Richard Chang
IPC分类号： G06F1/08 , G06F1/06 , G06F1/10 , H03K5/13 , H03K19/173 , H03L7/08 , H03L7/081 , H03L7/099 , H03L7/18 , H04J3/06 , H03L7/06
CPC分类号： H03L7/18 , H03L7/081 , H03L7/0996
摘要： A programmable logic device includes configurable phase-locked loop (PLL) circuitry that outputs multiple clock signals having programmable phases and frequencies. Each output signal is programmably selectable for use as an external clock, internal global clock, internal local clock, or combinations thereof. The PLL circuitry has programmable frequency dividing, including programmable cascaded frequency dividing, and programmable output signal multiplexing that provide a high degree of clock design flexibility.
摘要翻译：可编程逻辑器件包括可配置的锁相环（PLL）电路，其输出具有可编程相位和频率的多个时钟信号。每个输出信号可编程选择用作外部时钟，内部全局时钟，内部本地时钟或其组合。 PLL电路具有可编程分频，包括可编程级联分频，以及提供高度时钟设计灵活性的可编程输出信号复用。

2. 发明申请

US20060250168A1 Highly configurable PLL architecture for programmable logic 有权
公开(公告)号：US20060250168A1
公开(公告)日：2006-11-09
申请号：US11486565
申请日：2006-07-13
申请人： Gregory Starr , Wanli Chang , Kang Lai , Mian Smith , Richard Chang
发明人： Gregory Starr , Wanli Chang , Kang Lai , Mian Smith , Richard Chang
IPC分类号： H03L7/06
CPC分类号： H03L7/18 , H03L7/081 , H03L7/0996
摘要： A programmable logic device includes configurable phase-locked loop (PLL) circuitry that outputs multiple clock signals having programmable phases and frequencies. Each output signal is programmably selectable for use as an external clock, internal global clock, internal local clock, or combinations thereof. The PLL circuitry has programmable frequency dividing, including programmable cascaded frequency dividing, and programmable output signal multiplexing that provide a high degree of clock design flexibility.

3. 发明申请

US20050030114A1 Analog implementation of spread spectrum frequency modulation in a programmable phase locked loop (PLL) system 有权
标题翻译：在可编程锁相环（PLL）系统中模拟实现扩频调频
公开(公告)号：US20050030114A1
公开(公告)日：2005-02-10
申请号：US10888549
申请日：2004-07-09
申请人： Gregory Starr , Wanli Chang
发明人： Gregory Starr , Wanli Chang
IPC分类号： H03L7/089 , H03L7/093 , H03L7/18 , H03M1/80 , H04B1/707 , H04L7/033 , H03B29/00
CPC分类号： H03L7/0896 , H03L7/0898 , H03L7/093 , H03L7/18 , H03L7/1803 , H03M1/808 , H04B1/707
摘要： A PLL circuit is described. The PLL circuit includes: a signal generator; and a spread spectrum modulator coupled to the signal generator, where the spread spectrum modulator receives a control voltage as an input and provides a spread spectrum control voltage to the signal generator in response to the control voltage. In one embodiment, the spread spectrum modulator includes at least one selector, where the at least one selector selects a plurality of voltage levels that correspond to a spread mode and percentage of spread for the spread spectrum modulator.
摘要翻译：描述PLL电路。 PLL电路包括：信号发生器; 以及耦合到信号发生器的扩频调制器，其中扩频调制器接收控制电压作为输入，并且响应于控制电压向信号发生器提供扩频控制电压。在一个实施例中，扩频调制器包括至少一个选择器，其中至少一个选择器选择对应于扩展模式的多个电压电平和扩展频谱调制器的扩展百分比。

4. 发明授权

US06832173B1 Testing circuit and method for phase-locked loop 失效
标题翻译：锁相环测试电路及方法
公开(公告)号：US06832173B1
公开(公告)日：2004-12-14
申请号：US10209633
申请日：2002-07-30
申请人： Gregory Starr , Wanli Chang
发明人： Gregory Starr , Wanli Chang
IPC分类号： G01R3500
CPC分类号： H03L7/0891 , H03L7/0896
摘要： A testing circuit and method for a phase-locked loop allow measurement of leakage currents in the phase-locked loop components. By forcing the output of the phase-frequency detector to a particular state, the charge pump can be disabled. This disables the effect of feedback in the phase-locked loop, and allowing the output frequency to be determined by the voltage on the control voltage node at the time the feedback is disabled. If there is no leakage, the control voltage, and therefore the output frequency, should remain the same as they were at the moment feedback was disabled. Monitoring the output frequency for changes provides an indication of the presence or absence of leakage. Conducting the test using two different charge pump reference currents allows one to detect leakage resulting from charge pump mismatch.
摘要翻译：用于锁相环的测试电路和方法允许测量锁相环组件中的漏电流。通过将相频检测器的输出强制到特定状态，可以禁用电荷泵。这将禁止反相在锁相环中的影响，并允许输出频率由禁止反馈时控制电压节点上的电压决定。如果没有泄漏，则控制电压，因此输出频率应保持与反馈禁用时相同。监控变频器的输出频率提供有无泄漏的指示。使用两种不同的电荷泵参考电流进行测试可以检测电荷泵不匹配造成的泄漏。

5. 发明授权

US07098707B2 Highly configurable PLL architecture for programmable logic 有权
标题翻译：用于可编程逻辑的高度可配置的PLL架构
公开(公告)号：US07098707B2
公开(公告)日：2006-08-29
申请号：US10797836
申请日：2004-03-09
申请人： Gregory W. Starr , Wanli Chang , Kang Wei Lai , Mian Z. Smith , Richard Chang
发明人： Gregory W. Starr , Wanli Chang , Kang Wei Lai , Mian Z. Smith , Richard Chang
IPC分类号： H03L7/06
CPC分类号： H03L7/18 , H03L7/081 , H03L7/0996
摘要： A programmable logic device includes configurable phase-locked loop (PLL) circuitry that outputs multiple clock signals having programmable phases and frequencies. Each output signal is programmably selectable for use as an external clock, internal global clock, internal local clock, or combinations thereof. The PLL circuitry has programmable frequency dividing, including programmable cascaded frequency dividing, and programmable output signal multiplexing that provide a high degree of clock design flexibility.
摘要翻译：可编程逻辑器件包括可配置的锁相环（PLL）电路，其输出具有可编程相位和频率的多个时钟信号。每个输出信号可编程选择用作外部时钟，内部全局时钟，内部本地时钟或其组合。 PLL电路具有可编程分频，包括可编程级联分频，以及提供高度时钟设计灵活性的可编程输出信号复用。

6. 发明申请

US20070008000A1 Passgate structures for use in low-voltage applications 有权
标题翻译： Passgate结构用于低压应用
公开(公告)号：US20070008000A1
公开(公告)日：2007-01-11
申请号：US11498214
申请日：2006-08-01
申请人： Andy Lee , Wanli Chang , Cameron McClintock , John Turner , Brian Johnson , Chiao Hwang , Richard Chang , Richard Cliff
发明人： Andy Lee , Wanli Chang , Cameron McClintock , John Turner , Brian Johnson , Chiao Hwang , Richard Chang , Richard Cliff
IPC分类号： H03K19/177
CPC分类号： H03K19/17736 , H03K17/063 , H03K19/177 , H03K19/1778
摘要： Enhanced passgate structures for use in low-voltage systems are presented in which the influence of Vt on the range of signals passed by single-transistor passgates is reduced. In one arrangement, the VGATE-Vt limit for signals propagated through NMOS passgates is raised by applying a higher VGATE; in another arrangement, the Vt is lowered. The use of CMOS passgates in applications where single-transistor passgates have traditionally been used is also presented.
摘要翻译：提出了用于低电压系统的增强型门控结构，其中V 对由单晶闸管通过的信号范围的影响减小。在一种布置中，通过施加更高的V门极来提高通过NMOS通孔传播的信号的V门极限极限。在另一种布置中，V 降低。传统上使用单通道闸门的CMOS传动闸门的使用也被提出。

7. 发明授权

US07276943B2 Highly configurable PLL architecture for programmable logic 有权
标题翻译：用于可编程逻辑的高度可配置的PLL架构
公开(公告)号：US07276943B2
公开(公告)日：2007-10-02
申请号：US11486565
申请日：2006-07-13
申请人： Gregory W. Starr , Wanli Chang , Kang Wei Lai , Mian Z. Smith , Richard Chang
发明人： Gregory W. Starr , Wanli Chang , Kang Wei Lai , Mian Z. Smith , Richard Chang
IPC分类号： H03L7/06
CPC分类号： H03L7/18 , H03L7/081 , H03L7/0996
摘要： A programmable logic device includes configurable phase-locked loop (PLL) circuitry that outputs multiple clock signals having programmable phases and frequencies. Each output signal is programmably selectable for use as an external clock, internal global clock, internal local clock, or combinations thereof. The PLL circuitry has programmable frequency dividing, including programmable cascaded frequency dividing, and programmable output signal multiplexing that provide a high degree of clock design flexibility.
摘要翻译：可编程逻辑器件包括可配置的锁相环（PLL）电路，其输出具有可编程相位和频率的多个时钟信号。每个输出信号可编程选择用作外部时钟，内部全局时钟，内部本地时钟或其组合。 PLL电路具有可编程分频，包括可编程级联分频，以及提供高度时钟设计灵活性的可编程输出信号复用。

8. 发明授权

US5828229A Programmable logic array integrated circuits 失效
标题翻译：可编程逻辑阵列集成电路
公开(公告)号：US5828229A
公开(公告)日：1998-10-27
申请号：US847004
申请日：1997-05-01
申请人： Richard G. Cliff , L. Todd Cope , Cameron McClintock , William Leong , James Allen Watson , Joseph Huang , Bahram Ahanin , Chiakang Sung , Wanli Chang
发明人： Richard G. Cliff , L. Todd Cope , Cameron McClintock , William Leong , James Allen Watson , Joseph Huang , Bahram Ahanin , Chiakang Sung , Wanli Chang
IPC分类号： G01R31/3185 , G11C8/12 , G11C8/16 , G11C29/32 , H03K19/173 , H03K19/177
CPC分类号： H03K19/1737 , G11C29/32 , G11C8/12 , G11C8/16 , H03K19/17704 , H03K19/17728 , H03K19/1776 , H03K19/17764 , G01R31/318516
摘要： A programmable logic array integrated circuit has a number of programmable logic modules which are grouped together in a plurality of logic array blocks ("LABs"). The LABs are arranged on the circuit in a two dimensional array. A conductor network is provided for interconnecting any logic module with any other logic module. In addition, adjacent or nearby logic modules are connectable to one another for such special purposes as providing a carry chain between logic modules and/or for connecting two or more modules together to provide more complex logic functions without having to make use of the general interconnection network. Another network of so-called fast or universal conductors is provided for distributing widely used logic signals such as clock and clear signals throughout the circuit. Multiplexers can be used in various ways to reduce the number of programmable interconnections required between signal conductors. A relatively large block of random access memory ("RAM") may be provided on the device for use as read-only memory ("ROM") or RAM during operation of the device to perform logic. The RAM block is connected in the circuitry of the device so that it can be programmed and verified compatibly with other memory on the device. Thereafter the circuitry of the RAM block allows it to be switched over to operation as RAM or ROM during logic operation of the device.
摘要翻译：可编程逻辑阵列集成电路具有多个可编程逻辑模块，它们被组合在多个逻辑阵列块（“LAB”）中。 LAB以二维阵列布置在电路上。提供一个导线网络，用于将任何逻辑模块与任何其他逻辑模块相互连接。此外，相邻或附近的逻辑模块可以彼此连接，用于在逻辑模块之间提供进位链和/或用于将两个或多个模块连接在一起以提供更复杂的逻辑功能而不必利用一般互连的特殊目的网络。提供了所谓的快速或通用导体的另一网络，用于在整个电路中分布广泛使用的逻辑信号，例如时钟和清除信号。多路复用器可以以各种方式用于减少信号导体之间所需的可编程互连数量。随机存取存储器（“RAM”）相对较大的块可以在设备的操作期间被提供在设备上用作只读存储器（“ROM”）或RAM，以执行逻辑。 RAM块连接在设备的电路中，使其可以与设备上的其他存储器进行编程和验证。此后，RAM块的电路允许在设备的逻辑运行期间将其切换到作为RAM或ROM的操作。

9. 发明授权

US5633830A Random access memory block circuitry for programmable logic array integrated circuit devices 失效
标题翻译：用于可编程逻辑阵列集成电路器件的随机存取存储器块电路
公开(公告)号：US5633830A
公开(公告)日：1997-05-27
申请号：US555106
申请日：1995-11-08
申请人： Chiakang Sung , Wanli Chang , Joseph Huang , Richard G. Cliff
发明人： Chiakang Sung , Wanli Chang , Joseph Huang , Richard G. Cliff
IPC分类号： G01R31/3185 , G11C8/12 , G11C8/16 , G11C29/32 , H03K19/173 , H03K19/177 , G11C7/00
CPC分类号： H03K19/1737 , G11C29/32 , G11C8/12 , G11C8/16 , H03K19/17704 , H03K19/17728 , H03K19/1776 , H03K19/17764 , G01R31/318516
摘要： A relatively large block of random access memory ("RAM") may be provided on a programmable logic array integrated circuit device for use as read-only memory ("ROM") or RAM during operation of the device to perform logic. The RAM block is connected in the circuitry of the device so that it can be programmed and verified compatibly with other memory on the device. Thereafter the circuitry of the RAM block allows it to be switched over to operation as RAM or ROM during logic operation of the device.
摘要翻译：可以在可编程逻辑阵列集成电路装置上提供相对较大的随机存取存储器块（“RAM”），用于在设备操作期间用作只读存储器（“ROM”）或RAM以执行逻辑。 RAM块连接在设备的电路中，使其可以与设备上的其他存储器进行编程和验证。此后，RAM块的电路允许在设备的逻辑运行期间将其切换到作为RAM或ROM的操作。

10. 发明授权

US5555214A Apparatus for serial reading and writing of random access memory arrays 失效
标题翻译：用于串行读取和写入随机存取存储器阵列的装置
公开(公告)号：US5555214A
公开(公告)日：1996-09-10
申请号：US555110
申请日：1995-11-08
申请人： Chiakang Sung , Wanli Chang , Joseph Huang
发明人： Chiakang Sung , Wanli Chang , Joseph Huang
IPC分类号： G11C7/10 , G11C7/22 , G11C7/00
CPC分类号： G11C7/103 , G11C7/22
摘要： A method of serially reading and writing random access memory arrays is provided. Although the read/write inputs continually change as programming data are clocked into the input buffers, a read/write control circuit prevents the constantly changing read/write inputs from causing undesired reading and writing.
摘要翻译：提供了串行读取和写入随机存取存储器阵列的方法。尽管读/写输入随着编程数据被输入到输入缓冲器而不断变化，但读/写控制电路可以防止不断变化的读/写输入引起不期望的读和写。

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