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1. 发明申请

US20080014678A1 System and method of attenuating electromagnetic interference with a grounded top film 审中-公开
标题翻译：衰减与接地顶层电磁干扰的系统和方法
公开(公告)号：US20080014678A1
公开(公告)日：2008-01-17
申请号：US11486711
申请日：2006-07-14
申请人： Gregory Eric Howard , Vikas Gupta , Wilmar Sibido
发明人： Gregory Eric Howard , Vikas Gupta , Wilmar Sibido
IPC分类号： H01L21/00
CPC分类号： H01L23/552 , H01L21/565 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/85 , H01L24/97 , H01L2224/16225 , H01L2224/45144 , H01L2224/48091 , H01L2224/4813 , H01L2224/48464 , H01L2224/48599 , H01L2224/4917 , H01L2224/85 , H01L2224/97 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01057 , H01L2924/01078 , H01L2924/01079 , H01L2924/12041 , H01L2924/14 , H01L2924/181 , H01L2924/19107 , H01L2924/3025 , H01L2224/78 , H01L2924/00 , H01L2224/81 , H01L2224/85399 , H01L2224/05599
摘要： A plastic integrated circuit package often includes one or more integrated circuit elements that are sensitive to outside electromagnetic fields and also may generate electromagnetic fields that may interfere with other circuits outside of the package. The package herein has a top metal film to attenuate such electromagnetic fields, using a wire loop extending through the encapsulating compound to the metal film on top of encapsulating compound to provide electrical connection between top EMI film and end-and-ground junctions at grounds on die or on end-and-ground junctions at grounds on substrate.
摘要翻译：塑料集成电路封装通常包括对外部电磁场敏感的一个或多个集成电路元件，并且还可以产生可能干扰封装外部的其它电路的电磁场。本文中的封装具有顶部金属膜，以使这种电磁场衰减，使用延伸穿过封装化合物的导线环到封装化合物顶部的金属膜，以在顶部EMI膜和末端和接地之间的接地处提供电连接在基底上的地面上死亡或在地面接地处。

2. 发明申请

US20080220590A1 Thin wafer dicing using UV laser 审中-公开
标题翻译：使用紫外激光的薄晶片切割
公开(公告)号：US20080220590A1
公开(公告)日：2008-09-11
申请号：US11714345
申请日：2007-03-06
申请人： Mikel R. Miller , Vikas Gupta , Gregory Eric Howard
发明人： Mikel R. Miller , Vikas Gupta , Gregory Eric Howard
IPC分类号： H01L21/00 , B23K26/04
CPC分类号： B23K26/03 , B23K26/0626 , B23K26/073 , B23K26/08 , B23K26/0853 , B23K26/38 , B23K26/40 , B23K2101/40 , B23K2103/50 , H01L21/67092
摘要： In a method and system for dicing a wafer (220), an ultraviolet (UV) laser (210) is aligned with a street (222) on the wafer (220). A thickness of the wafer (220) is at most 400 times a wavelength of the UV laser (210). When energized, the UV laser (210) generates an adjustable amount of energy in the form of a plurality of laser pulses (212) that are focused on the street (222). The amount of energy provided to the wafer (220) is adjustable in accordance to the thickness. The plurality of laser pulses (212) perform the dicing of the wafer (220) along the street (222) by ablating material from the wafer (220).
摘要翻译：在用于切割晶片（220）的方法和系统中，紫外线（UV）激光器（210）与晶片（220）上的街道（222）对准。晶片（220）的厚度为UV激光器（210）的波长的至多400倍。当通电时，UV激光器（210）以聚焦在街道（222）上的多个激光脉冲（212）的形式产生可调量的能量。提供给晶片（220）的能量的量可根据厚度进行调整。多个激光脉冲（212）通过从晶片（220）烧蚀材料来执行沿着街道（222）的晶片（220）的切割。

3. 发明申请

US20090026605A1 Heat Extraction from Packaged Semiconductor Chips, Scalable with Chip Area 有权
标题翻译：封装半导体芯片的热提取，可扩展芯片面积
公开(公告)号：US20090026605A1
公开(公告)日：2009-01-29
申请号：US11828853
申请日：2007-07-26
申请人： Vikas Gupta , Siva P. Gurrum , Gregory Eric Howard
发明人： Vikas Gupta , Siva P. Gurrum , Gregory Eric Howard
IPC分类号： H01L23/34 , H01L21/00
CPC分类号： H01L23/3677 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2224/05553 , H01L2224/05624 , H01L2224/05644 , H01L2224/45015 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/48599 , H01L2224/48699 , H01L2224/4903 , H01L2224/73265 , H01L2924/01006 , H01L2924/01012 , H01L2924/01013 , H01L2924/01019 , H01L2924/0102 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01327 , H01L2924/14 , H01L2924/181 , H01L2924/20751 , H01L2924/20753 , H01L2924/20754 , H01L2924/20755 , H01L2924/01004 , H01L2924/01026 , H01L2924/00014 , H01L2924/20752 , H01L2924/00012
摘要： A semiconductor device (100A) with plastic encapsulation compound (102) and metal sheets (103a and 104) on both surfaces, acting as heat spreaders. One or more thermal conductors (103a) of preferably uniform height connect one sheet (103b) and the chip surface (101a); the number of conductors is scalable with the chip size. Each conductor consists of an elongated wire loop (preferably copper) with the wire ends attached to a pad (105), preferably both ends to the same pad. The major loop diameter is approximately normal to the first surface and the loop vertex in contact with the sheet (103b). The substrate (104, preferably a second metal sheet) covers at least portions of the second package surface and is thermally conductively connected to the chip.
摘要翻译：一种具有塑料封装化合物（102）和两个表面上的金属片（103a和104）的半导体器件（100A），用作散热器。一个或多个优选均匀高度的热导体（103a）连接一片（103b）和芯片表面（101a）; 导体的数量可随芯片尺寸而变化。每个导体由细长的线环（优选为铜）组成，线末端连接到衬垫（105），优选两端连接至相同的衬垫。主环直径大致垂直于第一表面，并且环形顶点与片材（103b）接触。衬底（104，优选地是第二金属片）覆盖第二封装表面的至少一部分并且导热连接到芯片。

4. 发明申请

US20080079159A1 Focused stress relief using reinforcing elements 审中-公开
标题翻译：使用增强元素集中应力消除
公开(公告)号：US20080079159A1
公开(公告)日：2008-04-03
申请号：US11542336
申请日：2006-10-02
申请人： Vikas Gupta , Gregory Eric Howard
发明人： Vikas Gupta , Gregory Eric Howard
IPC分类号： H01L23/52 , H01L21/4763
CPC分类号： H01L23/53295 , H01L23/585 , H01L2224/05124 , H01L2224/05147 , H01L2224/05166 , H01L2224/05184 , H01L2224/0557 , H01L2224/05571 , H01L2224/05573 , H01L2224/0558 , H01L2224/05644 , H01L2224/05664 , H01L2224/05669 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/00 , H01L2924/00014 , H01L2924/013
摘要： In a method and system for relieving stress induced within a dielectric layer of a semiconductor device (100), areas in the dielectric layer (236, 238, 242) where the stress exceeds a threshold are identified. The areas, which are in parallel alignment with electrical interconnects such as conductive bumps (130), include a selected number of outer rows of the conductive bumps (130) having a high stress level. Within the identified areas where the stress exceeds the threshold, patterned zones (250) having an adjustable zone density are provided by adding reinforcing elements (240) to relieve the stress below the threshold.
摘要翻译：在用于减轻在半导体器件（100）的电介质层内感应的应力的方法和系统中，识别出应力超过阈值的电介质层（236,238,242）中的区域。与诸如导电凸块（130）的电互连平行对准的区域包括具有高应力水平的选定数量的导电凸块（130）的外排。在应力超过阈值的识别区域内，通过添加增强元件（240）以减轻低于阈值的应力来提供具有可调区域密度的图案区域（250）。

5. 发明授权

US07132359B2 Tolerance bondwire inductors for analog circuitry 有权
标题翻译：用于模拟电路的公差接线电感
公开(公告)号：US07132359B2
公开(公告)日：2006-11-07
申请号：US10984150
申请日：2004-11-09
申请人： Gregory Eric Howard , Naveen Yanduru
发明人： Gregory Eric Howard , Naveen Yanduru
IPC分类号： H01L21/44
CPC分类号： H01L24/85 , H01L24/48 , H01L24/49 , H01L2224/05554 , H01L2224/48227 , H01L2224/49171 , H01L2224/85 , H01L2924/00014 , H01L2924/01066 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , H01L2924/00 , H01L2224/45099 , H01L2224/05599
摘要： Disclosed are wirebonding methods wherein bondwires are positioned using dynamically determined variations in die placement. Preferred methods of the invention include steps for placing a die on the prepared substrate using selected ideal placement coordinates. Deviation of the actual die placement from the selected ideal placement coordinates is monitored, and one ore more critical bondwires are wirebonded between respective die pins and pins on the substrate. The monitored placement deviation is used to dynamically position the critical bondwires on the critical pins according to actual die placement. Disclosed embodiments include methods using lateral deviation monitoring and angular deviation monitoring to dynamically position bondwires.
摘要翻译：公开了引线键合方法，其中使用动态确定的管芯放置的变化来定位焊丝。本发明的优选方法包括使用选择的理想放置坐标将管芯放置在所制备的衬底上的步骤。监测实际管芯位置与所选择的理想放置坐标的偏差，并且一个或多个关键焊接线在相应的管芯引脚和衬底上的引脚之间引线键合。监控的放置偏差用于根据实际的管芯位置动态地将关键焊接线定位在关键销上。公开的实施例包括使用横向偏差监测和角度偏差监测来动态地定位键合线的方法。

6. 发明申请

US20140189628A1 SYSTEM AND METHOD OF CROSSOVER DETERMINATION IN DIFFERENTIAL PAIR AND BONDWIRE PAIRS TO MINIMIZE CROSSTALK 有权
标题翻译：不同配对和绑定对的裁判员确定系统和方法以最小化CROSSTALK
公开(公告)号：US20140189628A1
公开(公告)日：2014-07-03
申请号：US13728196
申请日：2012-12-27
申请人： Gregory Eric Howard , Andy Quang Tran , Yanli Fan , Kartheinz Muth
发明人： Gregory Eric Howard , Andy Quang Tran , Yanli Fan , Kartheinz Muth
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5077 , G06F2217/82
摘要： A system is provided for use with circuit layout design data having a set of differential pairs and a set of bond wire pairs. A layout portion can receive the circuit layout design data. A crosstalk calculating portion can determine a first amount of crosstalk in a circuit corresponding to the circuit layout design data. A modifier can modify the circuit layout design data into modified circuit layout design data such that one of the set of differential pairs and the set of bond wire pairs includes a crossover. The crosstalk calculating portion can further determine a second amount of crosstalk in a circuit corresponding to the modified circuit layout design data. An optimizer can compare the first amount of crosstalk with the second amount of crosstalk to generate optimized circuit layout design data. A layout designer can output the optimized circuit layout design data.
摘要翻译：提供了一种用于具有一组差分对和一组键合线对的电路布局设计数据的系统。布局部分可以接收电路布局设计数据。串扰计算部分可以确定与电路布局设计数据相对应的电路中的第一串扰量。修改器可以将电路布局设计数据修改为修改的电路布局设计数据，使得该组差分对和该组接合线对中的一个包括交叉。串扰计算部分还可以确定对应于修改的电路布局设计数据的电路中的第二串扰量。优化器可以将第一量级串扰与第二量级串扰进行比较，以产生优化的电路布局设计数据。布局设计师可以输出优化的电路布局设计数据。

7. 发明申请

US20140184350A1 TWO LAYER DIFFERENTIAL PAIR LAYOUT, AND METHOD OF MAKING THEREOF, FOR REDUCED CROSSTALK 审中-公开
标题翻译：两层差分配对布置及其制造方法，用于减少CROSSTALK
公开(公告)号：US20140184350A1
公开(公告)日：2014-07-03
申请号：US13728468
申请日：2012-12-27
申请人： Gregory Eric Howard
发明人： Gregory Eric Howard
IPC分类号： H01P3/08 , H01P11/00
CPC分类号： H01P3/08 , H01L2924/0002 , H01P3/026 , H01P11/003 , H05K1/0245 , H05K2201/09709 , H01L2924/00
摘要： A device is provided for use with a signal, wherein the device includes a substrate, a first signal trace and a second signal trace. The first signal trace is disposed within the substrate at a first plane from the top surface by a distance d1. The second signal trace is disposed within the substrate at a second plane from the top surface by a distance d2, wherein d2
摘要翻译：提供了一种与信号一起使用的装置，其中该装置包括一基板，一第一信号迹线和一第二信号迹线。第一信号迹线在距离顶部表面的第一平面处设置在衬底内距离d1。第二信号迹线在距离顶表面的第二平面处设置在衬底内距离d2，其中d2

8. 发明授权

US08531030B2 IC device having electromigration resistant feed line structures 有权
标题翻译：具有电迁移电源线结构的IC器件
公开(公告)号：US08531030B2
公开(公告)日：2013-09-10
申请号：US12970464
申请日：2010-12-16
申请人： Gregory Eric Howard , Patrick Thompson
发明人： Gregory Eric Howard , Patrick Thompson
IPC分类号： H01L23/48
CPC分类号： H01L24/05 , H01L23/528 , H01L24/13 , H01L2224/0401 , H01L2224/05093 , H01L2224/05094 , H01L2224/05096 , H01L2224/05124 , H01L2224/05572 , H01L2224/05647 , H01L2224/05655 , H01L2224/131 , H01L2224/13144 , H01L2224/13147 , H01L2224/1329 , H01L2224/133 , H01L2224/16225 , H01L2224/16227 , H01L2924/00014 , H01L2924/01029 , H01L2924/1305 , H01L2924/14 , H01L2924/1421 , H01L2924/1431 , H01L2924/1433 , H01L2924/1434 , H01L2924/1461 , H01L2924/014 , H01L2224/05552 , H01L2924/00
摘要： An integrated circuit (IC) device includes an electromigration resistant feed line. The IC device includes a substrate including active circuitry. A back end of the line (BEOL) metallization stack includes an interconnect metal layer that is coupled to a bond pad by the EM resistant feed line. A bonding feature is on the bond pad. The feed line includes a uniform portion and patterned trace portion that extends to the bond pad which includes at least three sub-traces that are electrically in parallel. The sub-traces are sized so that a number of squares associated with each of the sub-traces are within a range of a mean number of squares for the sub-traces plus or minus twenty percent or a current density provided to the bonding feature through each sub-trace is within a range of a mean current density provided to the bonding feature plus or minus twenty percent.
摘要翻译：集成电路（IC）装置包括电迁移馈电线。 IC器件包括包括有源电路的衬底。线的后端（BEOL）金属化堆叠包括互连金属层，其通过EM抗性馈送线耦合到接合焊盘。接合焊盘上粘接特性。馈送线包括均匀部分和图案化的迹线部分，其延伸到接合焊盘，其包括电并联的至少三个子迹线。子迹线的大小使得与每个子迹线相关联的多个正方形在子迹线的平均平方根的范围内加上或减去百分之二十或者提供给粘合特征的电流密度通过每个子迹线在提供给结合特征的平均电流密度的±20％的范围内。

9. 发明授权

US08769469B1 System and method of crossover determination in differential pair and bondwire pairs to minimize crosstalk 有权
标题翻译：在差分对和接线对中交叉确定的系统和方法，以尽可能减少串扰
公开(公告)号：US08769469B1
公开(公告)日：2014-07-01
申请号：US13728196
申请日：2012-12-27
申请人： Gregory Eric Howard , Andy Quang Tran , Yanli Fan , Kartheinz Muth
发明人： Gregory Eric Howard , Andy Quang Tran , Yanli Fan , Kartheinz Muth
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5077 , G06F2217/82
摘要： A system is provided for use with circuit layout design data having a set of differential pairs and a set of bond wire pairs. A layout portion can receive the circuit layout design data. A crosstalk calculating portion can determine a first amount of crosstalk in a circuit corresponding to the circuit layout design data. A modifier can modify the circuit layout design data into modified circuit layout design data such that one of the set of differential pairs and the set of bond wire pairs includes a crossover. The crosstalk calculating portion can further determine a second amount of crosstalk in a circuit corresponding to the modified circuit layout design data. An optimizer can compare the first amount of crosstalk with the second amount of crosstalk to generate optimized circuit layout design data. A layout designer can output the optimized circuit layout design data.
摘要翻译：提供了一种用于具有一组差分对和一组键合线对的电路布局设计数据的系统。布局部分可以接收电路布局设计数据。串扰计算部分可以确定与电路布局设计数据相对应的电路中的第一串扰量。修改器可以将电路布局设计数据修改为修改的电路布局设计数据，使得该组差分对和该组接合线对中的一个包括交叉。串扰计算部分还可以确定对应于修改的电路布局设计数据的电路中的第二串扰量。优化器可以将第一量级串扰与第二量级串扰进行比较，以产生优化的电路布局设计数据。布局设计师可以输出优化的电路布局设计数据。

10. 发明申请

US20120153458A1 IC DEVICE HAVING ELECTROMIGRATION RESISTANT FEED LINE STRUCTURES 有权
标题翻译：具有电力输送线结构的IC器件
公开(公告)号：US20120153458A1
公开(公告)日：2012-06-21
申请号：US12970464
申请日：2010-12-16
申请人： Gregory Eric Howard , Patrick Thompson
发明人： Gregory Eric Howard , Patrick Thompson
IPC分类号： H01L23/488 , H01L21/768
CPC分类号： H01L24/05 , H01L23/528 , H01L24/13 , H01L2224/0401 , H01L2224/05093 , H01L2224/05094 , H01L2224/05096 , H01L2224/05124 , H01L2224/05572 , H01L2224/05647 , H01L2224/05655 , H01L2224/131 , H01L2224/13144 , H01L2224/13147 , H01L2224/1329 , H01L2224/133 , H01L2224/16225 , H01L2224/16227 , H01L2924/00014 , H01L2924/01029 , H01L2924/1305 , H01L2924/14 , H01L2924/1421 , H01L2924/1431 , H01L2924/1433 , H01L2924/1434 , H01L2924/1461 , H01L2924/014 , H01L2224/05552 , H01L2924/00
摘要： An integrated circuit (IC) device includes an electromigration resistant feed line. The IC device includes a substrate including active circuitry. A back end of the line (BEOL) metallization stack includes an interconnect metal layer that is coupled to a bond pad by the EM resistant feed line. A bonding feature is on the bond pad. The feed line includes a uniform portion and patterned trace portion that extends to the bond pad which includes at least three sub-traces that are electrically in parallel. The sub-traces are sized so that a number of squares associated with each of the sub-traces are within a range of a mean number of squares for the sub-traces plus or minus twenty percent or a current density provided to the bonding feature through each sub-trace is within a range of a mean current density provided to the bonding feature plus or minus twenty percent.
摘要翻译：集成电路（IC）装置包括电迁移馈电线。 IC器件包括包括有源电路的衬底。线的后端（BEOL）金属化堆叠包括互连金属层，其通过EM抗性馈送线耦合到接合焊盘。接合焊盘上粘接特性。馈送线包括均匀部分和图案化的迹线部分，其延伸到接合焊盘，其包括电并联的至少三个子迹线。子迹线的大小使得与每个子迹线相关联的多个正方形在子迹线的平均平方根的范围内加上或减去百分之二十或者提供给粘合特征的电流密度通过每个子迹线在提供给结合特征的平均电流密度的±20％的范围内。

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