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1. 发明申请

US20090040857A1 INTEGRATED CIRCUIT INCLUDING DECOUPLING CAPACITORS THAT CAN BE DISABLED 审中-公开
标题翻译：集成电路，包括可以禁用的解耦电容
公开(公告)号：US20090040857A1
公开(公告)日：2009-02-12
申请号：US11835675
申请日：2007-08-08
申请人： Grant McNeil , Ernst Stahl
发明人： Grant McNeil , Ernst Stahl
IPC分类号： G11C5/14
CPC分类号： H01L27/0733 , G11C11/401 , G11C29/02 , G11C2029/5002 , G11C2029/5006 , H01L22/22 , H01L22/34 , H01L27/10844
摘要： An integrated circuit includes a decoupling capacitor configured to be enabled in response to the decoupling capacitor not increasing a standby current of the integrated circuit and disabled in response to the decoupling capacitor increasing the standby current of the integrated circuit.
摘要翻译：集成电路包括去耦电容器，其被配置为响应于去耦电容器而使得能够增加集成电路的待机电流并且响应于去耦电容器增加集成电路的待机电流而被禁用。

2. 发明授权

US06943396B2 Electro-static discharge protection circuit and method for making the same 失效
标题翻译：静电放电保护电路及其制作方法
公开(公告)号：US06943396B2
公开(公告)日：2005-09-13
申请号：US10464382
申请日：2003-06-17
申请人： Grant McNeil
发明人： Grant McNeil
IPC分类号： H01L23/60 , H01L23/62 , H01L27/00 , H01L27/02 , H01L27/085 , H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L27/0255 , H01L27/10841 , H01L27/10897
摘要： As disclosed herein, an electrostatic discharge (ESD) protection circuit is provided for an integrated circuit including a semiconductor substrate. The ESD protection circuit includes a plurality of active devices formed in the semiconductor substrate, the active devices being formed by a process including a plurality of steps carried out to form, at the same time, a plurality of active devices having a function other than ESD protection. For example, the ESD circuit may include an array of vertical transistors formed according to a process including many of the steps used to form, at the same time, vertical transistors of a DRAM array. Also disclosed is the formation of an ESD circuit in an “unusable” area of a semiconductor chip, such as under a bond pad, land or under bump metallization of the chip.
摘要翻译：如本文所公开的，为包括半导体衬底的集成电路提供了静电放电（ESD）保护电路。 ESD保护电路包括形成在半导体衬底中的多个有源器件，有源器件通过包括多个步骤的处理形成，同时形成具有除了ESD之外的功能的多个有源器件保护。例如，ESD电路可以包括根据包括用于同时形成DRAM阵列的垂直晶体管的许多步骤的工艺形成的垂直晶体管阵列。还公开了在半导体芯片的“不可用”区域中形成ESD电路，例如在焊盘下方，芯片的焊盘或凸块下方金属化。

3. 发明授权

US07257038B2 Test mode for IPP current measurement for wordline defect detection 有权
标题翻译：用于字线缺陷检测的IPP电流测量的测试模式
公开(公告)号：US07257038B2
公开(公告)日：2007-08-14
申请号：US11322252
申请日：2006-01-03
申请人： Michael A. Killian , Martin Versen , Grant McNeil , Zach Johnson , Changduk Kim
发明人： Michael A. Killian , Martin Versen , Grant McNeil , Zach Johnson , Changduk Kim
IPC分类号： G11C7/00
CPC分类号： G11C29/02 , G11C29/025 , G11C2029/1202 , G11C2029/5006
摘要： A semiconductor integrated circuit memory device, and test method for a memory device are provided in which an external wordline voltage is applied to a wordline of the memory device. A current on the wordline is measured as a result of application of the externally supplied wordline voltage. The measured current is compared to a reference value to determine whether the wordline has a defect, in particular a short-circuit defect. A tester device is connected to the memory device and supplies the external wordline voltage. The current measurement and comparison may be made internally by circuitry on the memory device or externally by circuitry in a tester device.
摘要翻译：提供一种半导体集成电路存储器件以及用于存储器件的测试方法，其中外部字线电压被施加到存储器件的字线。作为施加外部提供的字线电压的结果，测量字线上的电流。将测量的电流与参考值进行比较以确定字线是否具有缺陷，特别是短路缺陷。测试器设备连接到存储器件并提供外部字线电压。当前的测量和比较可以由存储器件上的电路或外部由测试仪器中的电路在内部进行。

4. 发明申请

US20070153596A1 Test mode for IPP current measurement for wordline defect detection 有权
公开(公告)号：US20070153596A1
公开(公告)日：2007-07-05
申请号：US11322252
申请日：2006-01-03
申请人： Michael Kilian , Martin Versen , Grant McNeil , Zach Johnson , Changduk Kim
发明人： Michael Kilian , Martin Versen , Grant McNeil , Zach Johnson , Changduk Kim
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： G11C29/02 , G11C29/025 , G11C2029/1202 , G11C2029/5006
摘要： A semiconductor integrated circuit memory device, and test method for a memory device are provided in which an external wordline voltage is applied to a wordline of the memory device. A current on the wordline is measured as a result of application of the externally supplied wordline voltage. The measured current is compared to a reference value to determine whether the wordline has a defect, in particular a short-circuit defect. A tester device is connected to the memory device and supplies the external wordline voltage. The current measurement and comparison may be made internally by circuitry on the memory device or externally by circuitry in a tester device.

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