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1. 发明授权

US06285697B1 Semiconductor laser component 有权
标题翻译：半导体激光元件
公开(公告)号：US06285697B1
公开(公告)日：2001-09-04
申请号：US09364896
申请日：1999-08-02
申请人： Gottfried Landwehr , Markus Keim , Günter Reuscher , Thomas Litz , Thierry Baron , Frank Fischer , Hans-Jürgen Lugauer
发明人： Gottfried Landwehr , Markus Keim , Günter Reuscher , Thomas Litz , Thierry Baron , Frank Fischer , Hans-Jürgen Lugauer
IPC分类号： H01S500
CPC分类号： B82Y20/00 , H01S5/0421 , H01S5/3054 , H01S5/3095 , H01S5/34313
摘要： A semiconductor laser component includes a semiconductor body with an SCH configuration which is suitable for generating an electromagnetic radiation and in which an active layer sequence with a quantum well structure is provided between a first outer cover layer of a first conductivity type and a second outer cover layer of the first conductivity type. A first denatured transition layer of a second conductivity type and a second denatured transition layer the first conductivity type are provided between the active layer sequence and the second outer cover layer.
摘要翻译：半导体激光器部件包括具有适合于产生电磁辐射的SCH配置的半导体本体，其中具有量子阱结构的有源层序列设置在第一导电类型的第一外覆盖层和第二外覆盖层之间第一导电类型的层。第一导电类型的第一变性过渡层和第二导电类型的第二变性过渡层设置在有源层序列和第二外覆层之间。

2. 发明授权

US06372536B1 II-VI semiconductor component having at least one junction between a layer containing Se and a layer containing BeTe, and process for producing the junction 失效
标题翻译： II-VI族半导体元件在含有Se的层和含有BeTe的层之间具有至少一个结，以及用于制造该结的工艺
公开(公告)号：US06372536B1
公开(公告)日：2002-04-16
申请号：US09480756
申请日：2000-01-10
申请人： Frank Fischer , Andreas Waag , Thierry Baron , Gottfried Landwehr , Thomas Litz , Günter Reuscher , Markus Keim , Ulrich Zehnder , Hans-Peter Steinbrück , Mario Nagelstrasser , Hans-Jürgen Lugauer
发明人： Frank Fischer , Andreas Waag , Thierry Baron , Gottfried Landwehr , Thomas Litz , Günter Reuscher , Markus Keim , Ulrich Zehnder , Hans-Peter Steinbrück , Mario Nagelstrasser , Hans-Jürgen Lugauer
IPC分类号： H01L2100
CPC分类号： H01L33/40 , H01L33/0087 , H01L33/28
摘要： The invention relates to a II-VI semiconductor component in which, within a series of layers, there is provided at least one junction between a semiconductor layer containing BeTe and a semiconductor layer containing Se. A boundary layer between the semiconductor layer containing BeTe and the semiconductor layer containing Se is prepared in such a way that it forms a Be—Se configuration.
摘要翻译：本发明涉及一种II-VI族半导体元件，其中在一系列层内提供了含有BeTe的半导体层和含有Se的半导体层之间的至少一个结。包含BeTe的半导体层和含有Se的半导体层之间的边界层以使其形成Be-Se构型的方式制备。

3. 发明授权

US06399473B1 Method of producing a II-VI semiconductor component containing selenium and/or sulrfur 失效
标题翻译：制备含有硒和/或磺胺的II-VI半导体组分的方法
公开(公告)号：US06399473B1
公开(公告)日：2002-06-04
申请号：US09480758
申请日：2000-01-10
申请人： Frank Fischer , Matthias Keller , Thomas Litz , Gottfried Landwehr , Hans-Jürgen Lugauer , Andreas Waag , Markus Keim
发明人： Frank Fischer , Matthias Keller , Thomas Litz , Gottfried Landwehr , Hans-Jürgen Lugauer , Andreas Waag , Markus Keim
IPC分类号： H01L2128
CPC分类号： H01L21/02395 , H01L21/02439 , H01L21/0248 , H01L21/02485 , H01L21/02505 , H01L21/02557 , H01L21/0256 , H01L21/02631 , H01S5/327
摘要： A II-VI semiconductor component is produced with an active layer sequence having at least one II-VI semiconductor layer containing Se and/or S on a substrate. First, an Se-free II-VI interlayer based on BeTe is grown epitaxially on the substrate in an essentially Se-free and S-free first epitaxy chamber. The active layer sequence is then grown epitaxially on the Se-free II-VI semiconductor layer.
摘要翻译：制备具有在衬底上具有含有Se和/或S的至少一个II-VI半导体层的有源层序列的II-VI半导体元件。首先，在基本上不含Se的无S的第一外延室中，在衬底上外延生长基于BeTe的无Se的II-VI中间层。然后在无Se的II-VI半导体层上外延生长活性层序列。

4. 发明授权

US6147365A Optoelectronic semiconductor component 有权
标题翻译：光电半导体元件
公开(公告)号：US6147365A
公开(公告)日：2000-11-14
申请号：US364898
申请日：1999-08-02
申请人： Frank Fischer , Thomas Litz , Hans-Jurgen Lugauer , Markus Keim , Thierry Baron , Gunter Reuscher , Gottfried Landwehr
发明人： Frank Fischer , Thomas Litz , Hans-Jurgen Lugauer , Markus Keim , Thierry Baron , Gunter Reuscher , Gottfried Landwehr
IPC分类号： H01L33/00 , H01S5/042 , H01S5/30 , H01S5/34 , H01S5/347 , H01L29/22 , H01L31/0256
CPC分类号： B82Y20/00 , H01S5/305 , H01S5/347 , H01S5/0421 , H01S5/3059 , H01S5/3409
摘要： An optoelectronic semiconductor component has a radiation-emitting active layer sequence which is associated with at least one poorly dopable semiconductor layer of a first conductivity type. A heavily doped first degenerated junction layer of a first conductivity type and a heavily doped second degenerated junction layer of a second conductivity type opposite to the first conductivity type are provided between the poorly dopable semiconductor layer and a contact layer of the semiconductor body, the contact layer being associated with the poorly dopable semiconductor layer.
摘要翻译：光电子半导体部件具有辐射发射有源层序列，其与至少一个第一导电类型的不良掺杂半导体层相关联。第一导电类型的重掺杂第一退化结层和与第一导电类型相反的第二导电类型的重掺杂第二退化结层设置在不良掺杂半导体层和半导体本体的接触层之间，接触层与差的可掺杂半导体层相关联。

5. 发明授权

US06495859B2 Opto-electronic component made from II-VI semiconductor material 有权
标题翻译：由II-VI半导体材料制成的光电元件
公开(公告)号：US06495859B2
公开(公告)日：2002-12-17
申请号：US09876768
申请日：2001-06-07
申请人： Frank Fischer , Hans-Jürgen Lugauer , Thomas Litz , Gottfried Landwehr , Andreas Waag
发明人： Frank Fischer , Hans-Jürgen Lugauer , Thomas Litz , Gottfried Landwehr , Andreas Waag
IPC分类号： H01L3300
CPC分类号： H01S5/347 , B82Y20/00 , H01L33/0087 , H01L33/04 , H01L33/06 , H01L33/105 , H01L33/28 , H01L33/40 , H01S5/0421 , H01S5/18341 , H01S5/3063 , H01S5/3211 , H01S5/3215 , H01S5/3216 , H01S5/327
摘要： A component has an active layer, barrier layers and, if appropriate, a buffer layer and at least one of these layers contains a beryllium-containing chalcogenide. The active layer is a multiple layer, for example a superlattice made of BeTe/ZnSe or of BeTe/ZnCdSe. When using an active layer of ZnSe on a substrate of GaAs, matching with low electrical resistance is achieved between the III-V materials and the II-VI materials by means of a pseudo-graded buffer layer including a beryllium-containing chalcogenide.
摘要翻译：组分具有活性层，阻挡层，并且如果合适，具有缓冲层，并且这些层中的至少一层含有含铍的硫族化物。有源层是多层，例如由BeTe / ZnSe或BeTe / ZnCdSe制成的超晶格。当在GaAs衬底上使用ZnSe的活性层时，通过含有铍的硫族化物的假梯度缓冲层，在III-V材料和II-VI材料之间实现与低电阻的匹配。

6. 发明授权

US06265734B1 Opto-electronic component made from II-VI semiconductor material 失效
标题翻译：由II-VI半导体材料制成的光电元件
公开(公告)号：US06265734B1
公开(公告)日：2001-07-24
申请号：US09068138
申请日：1998-05-01
申请人： Frank Fischer , Hans-Jürgen Lugauer , Thomas Litz , Gottfried Landwehr , Andreas Waag
发明人： Frank Fischer , Hans-Jürgen Lugauer , Thomas Litz , Gottfried Landwehr , Andreas Waag
IPC分类号： H01L3300
CPC分类号： H01S5/347 , B82Y20/00 , H01L33/0087 , H01L33/04 , H01L33/06 , H01L33/105 , H01L33/28 , H01L33/40 , H01S5/0421 , H01S5/18341 , H01S5/3063 , H01S5/3211 , H01S5/3215 , H01S5/3216 , H01S5/327
摘要： Component having an active layer (4), barrier layers (3, 5), and, if appropriate, a buffer layer (2), of which layers at least one contains a beryllium-containing chalcogenide. The active layer is a multiple layer, for example a superlattice made of BeTE/ZnSe or of BeTe/ZnCdSe. When using an active layer of ZnSe on a substrate (1) of Gaps, matching with low electrical resistance is achieved between the III-V materials and the II-VI materials by means of a pseudo-graded buffer layer (2) including a beryllium-containing chalcogenide.
摘要翻译：具有活性层（4），阻挡层（3,5）以及如果适当的缓冲层（2）的组分，其中至少一层含有含铍的硫族化物。活性层是多层，例如由BeTE / ZnSe或BeTe / ZnCdSe制成的超晶格。当在间隙的衬底（1）上使用ZnSe的有源层时，通过包括铍的假级梯度缓冲层（2）在III-V材料和II-VI材料之间实现与低电阻的匹配含硫属化物。

7. 发明授权

US06618410B1 Optoelectronic semiconductor component 有权
标题翻译：光电半导体元件
公开(公告)号：US06618410B1
公开(公告)日：2003-09-09
申请号：US09455603
申请日：1999-12-06
申请人： Frank Fischer , Günter Reuscher , Thomas Litz , Gottfried Landwehr
发明人： Frank Fischer , Günter Reuscher , Thomas Litz , Gottfried Landwehr
IPC分类号： H01S500
CPC分类号： H01S5/183 , H01S5/18305 , H01S5/3095
摘要： An Optoelectronic semiconductor component, in which an active zone is disposed above a semiconductor substrate, and which zone is disposed between at least one first resonator mirror layer and at least one second resonator mirror layer. The first and the second mirror layer each have a semiconductor material of a first conductivity type. At least one first heavily doped junction layer of the first conductivity type and at least one second heavily doped junction layer of a second conductivity type are disposed between the active zone and one of the two mirror layers in such a way that the second heavily doped, degenerate junction layer lies between the active zone and the first heavily doped, degenerate junction layer.
摘要翻译：一种光电子半导体部件，其中有源区域设置在半导体衬底上方，并且该区域设置在至少一个第一谐振器镜面层和至少一个第二谐振器镜像层之间。第一和第二镜层各自具有第一导电类型的半导体材料。第一导电类型的至少一个第一重掺杂结层和第二导电类型的至少一个第二重掺杂结层被设置在有源区和两个镜层中的一个之间，使得第二重掺杂，简并结层位于有源区和第一重掺杂的退化结层之间。

8. 发明授权

US08941193B2 Method for manufacturing a hybrid integrated component 有权
标题翻译：混合集成部件的制造方法
公开(公告)号：US08941193B2
公开(公告)日：2015-01-27
申请号：US13869428
申请日：2013-04-24
申请人： Jens Frey , Frank Fischer
发明人： Jens Frey , Frank Fischer
IPC分类号： B81C3/00 , B81B1/00 , H01L29/84 , B81C1/00 , B81B7/00
CPC分类号： B81C1/00269 , B81B7/007 , B81C1/00238 , B81C2203/0785
摘要： A simple and cost-effective manufacturing method for hybrid integrated components including at least one MEMS element, a cap for the micromechanical structure of the MEMS element, and at least one ASIC substrate, using which a high degree of miniaturization may be achieved. The micromechanical structure of the MEMS element and the cap are manufactured in a layered structure, proceeding from a shared semiconductor substrate, by applying at least one cap layer to a first surface of the semiconductor substrate, and by processing and structuring the semiconductor substrate proceeding from its other second surface, to produce and expose the micromechanical MEMS structure. The semiconductor substrate is then mounted with the MEMS-structured second surface on the ASIC substrate.
摘要翻译：一种用于混合集成部件的简单和成本有效的制造方法，包括至少一个MEMS元件，用于MEMS元件的微机械结构的盖，以及至少一个ASIC基板，其可以实现高度的小型化。 MEMS元件和盖的微机械结构通过将至少一个盖层施加到半导体衬底的第一表面，并且通过加工和构造半导体衬底从共享半导体衬底开始，以分层结构制造，并且从其另一个第二表面，以产生和暴露微机械MEMS结构。然后将半导体衬底与MEMS结构的第二表面安装在ASIC衬底上。

9. 发明申请

US20140110800A1 Method for manufacturing a cap for a mems component, and hybrid integrated component having such a cap 有权
标题翻译：用于制造用于mems组件的盖的方法，以及具有这种盖的混合集成部件
公开(公告)号：US20140110800A1
公开(公告)日：2014-04-24
申请号：US14058806
申请日：2013-10-21
申请人： Johannes CLASSEN , Axel Franke , Jens Frey , Heribert Weber , Frank Fischer , Patrick Wellner
发明人： Johannes CLASSEN , Axel Franke , Jens Frey , Heribert Weber , Frank Fischer , Patrick Wellner
IPC分类号： B81C1/00 , B81B3/00
CPC分类号： B81C1/00015 , B81B3/0018 , B81B7/0058
摘要： A manufacturing method for a cap, for a hybrid vertically integrated component having a MEMS component a relatively large cavern volume having a low cavern internal pressure, and a reliable overload protection for the micromechanical structure of the MEMS component. A cap structure is produced in a flat cap substrate in a multistep anisotropic etching, and includes at least one mounting frame having at least one mounting surface and a stop structure, on the cap inner side, having at least one stop surface, the surface of the cap substrate being masked for the multistep anisotropic etching with at least two masking layers made of different materials, and the layouts of the masking layers and the number and duration of the etching steps being selected so that the mounting surface, the stop surface, and the cap inner side are situated at different surface levels of the cap structure.
摘要翻译：一种用于具有MEMS部件的混合垂直集成部件的盖的制造方法，具有较低的洞穴内部压力的相对较大的洞穴体积以及用于MEMS部件的微机械结构的可靠的过载保护。在多步骤各向异性蚀刻中，在平盖基板中制造盖结构，并且包括至少一个安装框架，该安装框架具有至少一个安装表面和止动结构，在盖内侧具有至少一个止动表面，掩模基板被掩模用于具有由不同材料制成的至少两个掩模层的多步各向异性蚀刻，并且选择掩模层的布局以及蚀刻步骤的数量和持续时间，使得安装表面，止动表面和帽内侧位于帽结构的不同表面水平处。

10. 发明申请

US20130299924A1 HYBRID INTEGRATED COMPONENT AND METHOD FOR THE MANUFACTURE THEREOF 有权
标题翻译：混合集成组件及其制造方法
公开(公告)号：US20130299924A1
公开(公告)日：2013-11-14
申请号：US13890450
申请日：2013-05-09
申请人： Heribert WEBER , Frank Fischer , Mirko Hattass , Yvonne Bergmann
发明人： Heribert WEBER , Frank Fischer , Mirko Hattass , Yvonne Bergmann
IPC分类号： B81B3/00 , B81C1/00
CPC分类号： B81B3/0021 , B81B2201/025 , B81B2207/096 , B81C1/00238 , B81C1/00261 , B81C1/00301 , B81C2203/0792 , H01L2224/13 , H01L2224/48463 , H01L2224/73257 , H01L2924/1461 , H01L2924/00
摘要： A component system includes at least one MEMS element, a cap for a micromechanical structure of the MEMS element, and at least one ASIC substrate. The micromechanical structure of the MEMS element is implemented in the functional layer of an SOI wafer. The MEMS element is mounted face down, with the structured functional layer on the ASIC substrate, and the cap is implemented in the substrate of the SOI wafer. The ASIC substrate includes a starting substrate provided with a layered structure on both sides. At least one circuit level is implemented in each case both in the MEMS-side layered structure and in the rear-side layered structure of the ASIC substrate. In the ASIC substrate, at least one ASIC through contact is implemented which electrically contacts at least one circuit level of the rear-side layered structure and/or at least one circuit level of the MEMS-side layered structure.
摘要翻译：组件系统包括至少一个MEMS元件，用于MEMS元件的微机械结构的盖以及至少一个ASIC基板。 MEMS元件的微机械结构在SOI晶片的功能层中实现。 MEMS元件面朝下安装，ASIC结构上的结构化功能层，并且帽被实现在SOI晶片的衬底中。 ASIC基板包括在两侧设置有分层结构的起始衬底。在ASIC基板的MEMS侧分层结构和后侧层叠结构中，每种情况都至少实现一个电路电平。在ASIC基板中，实现至少一个ASIC接触，其电接触后侧分层结构的至少一个电路电平和/或MEMS侧分层结构的至少一个电路电平。

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