专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20060152508A1 System and method for optimized specular highlight generation 失效
标题翻译：用于优化镜面高光生成的系统和方法
公开(公告)号：US20060152508A1
公开(公告)日：2006-07-13
申请号：US11032240
申请日：2005-01-10
申请人： Gordon Fossum , Stephen Schwinn , Matthew Tubbs
发明人： Gordon Fossum , Stephen Schwinn , Matthew Tubbs
IPC分类号： G06T15/50
CPC分类号： G06T15/506
摘要： A system and method for optimized specular highlight generation is presented. A single microprocessor instruction is used to generate an intensity value based upon a viewing angle value. An application stores a viewing angle value in an input register. When called, the “intensity instruction” retrieves the viewing angle value from the input register, and calculates an intensity value using three distinct steps. In turn, the intensity instruction stores the intensity value in an output register for the application to retrieve and further process. In one embodiment, the invention may be implemented using PowerPC™ assembly and VMX™ or Altivec™ instructions. In this embodiment, the intensity instruction may be represented as a “vspecefp” instruction, which stands for a “vector specular estimate floating point” instruction.
摘要翻译：提出了一种用于优化镜面高光生成的系统和方法。单个微处理器指令用于基于视角值产生强度值。应用程序将视角值存储在输入寄存器中。当被调用时，“强度指令”从输入寄存器检索视角值，并使用三个不同的步骤计算强度值。反之，强度指令将强度值存储在用于检索和进一步处理的应用的输出寄存器中。在一个实施例中，本发明可以使用PowerPC TM组件和VMX TM或Altivec TM指令来实现。在本实施例中，强度指令可以表示为“vspecefp”指令，其代表“矢量镜面估计浮点”指令。

2. 发明申请

US20050138095A1 Method for base two logarithmic estimation 审中-公开
标题翻译：基准二对数估计方法
公开(公告)号：US20050138095A1
公开(公告)日：2005-06-23
申请号：US10739427
申请日：2003-12-18
申请人： Gordon Fossum , Stephen Schwinn , Matthew Tubbs
发明人： Gordon Fossum , Stephen Schwinn , Matthew Tubbs
IPC分类号： G06F1/02 , G06F7/483 , G06F7/556
CPC分类号： G06F7/556 , G06F1/02 , G06F7/483 , G06F2101/10
摘要： The present invention provides for implementing a base two logarithmic estimation function in a general purpose processor. The present invention provides for partitioning an input value into a biased exponent value and a mantissa. Whether the biased exponent value is negative is determined. A first intermediate value from the mantissa is generated using custom combinational logic. A second intermediate value from the mantissa is generated using custom combinational logic. An unnormalized result fraction value from the first and second intermediate value and the mantissa is generated using custom combinational logic. This unnormalized result fraction and the unbiased exponent of the input are concatenated and normalized to form the final result.
摘要翻译：本发明提供了在通用处理器中实现基本两对数估计功能。本发明提供了将输入值划分为偏置指数值和尾数。确定偏置指数值是否为负。使用自定义组合逻辑生成来自尾数的第一个中间值。使用自定义组合逻辑生成来自尾数的第二个中间值。使用定制组合逻辑产生来自第一和第二中间值和尾数的非标准化结果分数值。这种非正规化结果分数和输入的无偏指数被连接并归一化以形成最终结果。

3. 发明申请

US20050091476A1 Apparatus for supporting a logically partitioned computer system 失效
标题翻译：用于支持逻辑分区计算机系统的装置
公开(公告)号：US20050091476A1
公开(公告)日：2005-04-28
申请号：US10948776
申请日：2004-09-23
申请人： Richard Doing , Ronald Kalla , Stephen Schwinn , Edward Silha , Kenichi Tsuchiya
发明人： Richard Doing , Ronald Kalla , Stephen Schwinn , Edward Silha , Kenichi Tsuchiya
IPC分类号： G06F9/38 , G06F12/02 , G06F12/10 , G06F12/14 , G06F15/00
CPC分类号： G06F9/3804 , G06F9/3842 , G06F9/3851 , G06F9/5077 , G06F12/0284 , G06F12/1036 , G06F12/109 , G06F12/1491
摘要： A processor supports logical partitioning of hardware resources including real address spaces of a computer system. An ultra-privileged supervisor process, called a hypervisor, regulates the logical partitions and can dynamically re-allocate resources. Preferably, the processor supports hardware multithreading, each thread independently capable of being in either hypervisor, supervisor, or problem state, and is capable of entering hypervisor state only upon occurrence of certain pre-defined events. A logical partition identifier is stored in a processor register, and can be altered by the processor only when in hypervisor state. Certain bus communications contain a logical partition identifier tag, and the processor ignores such communications if the tag does not match its own logical partition identifier in its register.
摘要翻译：处理器支持包括计算机系统的真实地址空间的硬件资源的逻辑分区。一个超级特权的管理程序称为虚拟机管理程序，可以调节逻辑分区，并可以动态重新分配资源。优选地，处理器支持硬件多线程，每个线程独立地能够处于管理程序，管理程序或问题状态中，并且仅在某些预定义事件发生时能够进入管理程序状态。逻辑分区标识符存储在处理器寄存器中，并且只有处于管理程序状态时才能被处理器改变。某些总线通信包含逻辑分区标识符标签，如果标记与其寄存器中的自己的逻辑分区标识符不匹配，则处理器忽略此类通信。

4. 发明申请

US20060095737A1 Methods and apparatus for pipelined processing 失效
标题翻译：流水线加工的方法和装置
公开(公告)号：US20060095737A1
公开(公告)日：2006-05-04
申请号：US10932730
申请日：2004-09-02
申请人： Stephen Schwinn
发明人： Stephen Schwinn
IPC分类号： G06F9/30
CPC分类号： G06F9/3836 , G06F9/384 , G06F9/3857
摘要： In a first aspect, a first method is provided for pipelined processing. The first method includes the steps of (1) receiving a first instruction in an in-order execution processing pipeline; and (2) receiving a second instruction in the in-order execution processing pipeline before execution of the first instruction completes. The second instruction depends on a control signal related to the first instruction. Numerous other aspects are provided.
摘要翻译：在第一方面，提供了一种用于流水线处理的第一种方法。第一种方法包括以下步骤：（1）在顺序执行处理流水线中接收第一指令; 以及（2）在第一指令执行完成之前在顺序执行处理流水线中接收第二指令。第二指令取决于与第一指令相关的控制信号。提供了许多其他方面。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式