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    • 2. 发明授权
    • Method and structure of ion implanted elements for the optimization of resistance
    • 用于优化电阻的离子注入元件的方法和结构
    • US07381582B2
    • 2008-06-03
    • US11263464
    • 2005-10-31
    • Russell L. JohnsonCurtis H. Rahn
    • Russell L. JohnsonCurtis H. Rahn
    • H01L21/00
    • G01L1/2293
    • A method of forming a piezo-resistive sensor, comprising a piezo-resistor, a leadout resistor, and an insulator structure is provided. A Silicon-On-Insulator (SOI) substrate is provided having an epitaxial layer, a dielectric layer, and a bulk substrate layer. A mask layer is formed on top of the epitaxial layer. The mask layer defines where the piezo-resistor and leadout resistors are to be located by creating first exposed portions of the epitaxial layer. A silicon dioxide layer (SiO2) is grown in a Local Oxidation of Silicon (LOCOS) process for a predetermined time on the first exposed portions based on the desired thickness of the piezo-resistor, where the-piezo resistor is located below the SiO2 layer. The thickness of the leadout resistor, and therefore the parasitic leadout resistance, is determined by the original thickness of the epitaxial layer and can be maintained independent of the piezo-resistor thickness.
    • 提供了一种形成压电传感器的方法,包括压电电阻器,引出电阻器和绝缘体结构。 提供具有外延层,电介质层和体基片层的绝缘体上硅绝缘体(SOI)衬底。 掩模层形成在外延层的顶部上。 掩膜层通过产生外延层的第一暴露部分来限定压电电阻器和引出电阻器将位于哪里。 基于压电电阻器的期望厚度,在第一暴露部分上在局部氧化硅(LOCOS)工艺中生长二氧化硅层(SiO 2)在预定时间内, 压电电阻器位于SiO 2层下方。 引出电阻的厚度,因此寄生引出电阻由外延层的原始厚度确定,并且可以独立于压电电阻器厚度来保持。