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1. 发明授权

US07589992B2 Semiconductor device having three dimensional structure 有权
标题翻译：具有三维结构的半导体器件
公开(公告)号：US07589992B2
公开(公告)日：2009-09-15
申请号：US11953289
申请日：2007-12-10
申请人： Gong-Heum Han , Hyou-Youn Nam , Bo-Tak Lim , Han-Byung Park , Soon-Moon Jung , Hoon Lim
发明人： Gong-Heum Han , Hyou-Youn Nam , Bo-Tak Lim , Han-Byung Park , Soon-Moon Jung , Hoon Lim
IPC分类号： G11C11/00
CPC分类号： G11C11/412 , H01L21/8221 , H01L27/0688 , H01L27/105 , H01L27/11 , H01L27/1108 , H01L27/1116
摘要： A semiconductor device and method for arranging and manufacturing the same are disclosed. The semiconductor device includes a plurality of inverters including at least one first pull-up transistor and first pull-down transistor and inverting and outputting an input signal, respectively; and a plurality of NAND gates including at least two second pull-up transistor and second pull-down transistor and generating an output signal having a high level if at least one of at least two input signals has a low level, respectively, wherein the at least one first pull-up transistor and first pull-down transistor and the at least two second pull-up transistor and second pull-down transistor are stacked and arranged on at least two layers.
摘要翻译：公开了一种半导体装置及其制造方法。半导体器件包括多个反相器，包括至少一个第一上拉晶体管和第一下拉晶体管，并分别反相并输出输入信号; 以及包括至少两个第二上拉晶体管和第二下拉晶体管的多个NAND门，并且如果至少两个输入信号中的至少一个分别具有低电平，则产生具有高电平的输出信号，其中at 至少一个第一上拉晶体管和第一下拉晶体管和至少两个第二上拉晶体管和第二下拉晶体管堆叠并布置在至少两层上。

2. 发明申请

US20090294863A1 Semiconductor Memory Device Having Three Dimensional Structure 有权
标题翻译：具有三维结构的半导体存储器件
公开(公告)号：US20090294863A1
公开(公告)日：2009-12-03
申请号：US12537521
申请日：2009-08-07
申请人： Gong-Heum Han , Hyou-Youn Nam , Bo-Tak Lim , Han-Byung Park , Soon-Moon Jung , Hoon Lim
发明人： Gong-Heum Han , Hyou-Youn Nam , Bo-Tak Lim , Han-Byung Park , Soon-Moon Jung , Hoon Lim
IPC分类号： H01L29/66
CPC分类号： G11C11/412 , H01L21/8221 , H01L27/0688 , H01L27/105 , H01L27/11 , H01L27/1108 , H01L27/1116
摘要： A semiconductor device and method for arranging and manufacturing the same are disclosed. The semiconductor device includes a plurality of inverters including at least one first pull-up transistor and first pull-down transistor and inverting and outputting an input signal, respectively; and a plurality of NAND gates including at least two second pull-up transistor and second pull-down transistor and generating an output signal having a high level if at least one of at least two input signals has a low level, respectively, wherein the at least one first pull-up transistor and first pull-down transistor and the at least two second pull-up transistor and second pull-down transistor are stacked and arranged on at least two layers.
摘要翻译：公开了一种半导体装置及其制造方法。半导体器件包括多个反相器，包括至少一个第一上拉晶体管和第一下拉晶体管，并分别反相并输出输入信号; 以及包括至少两个第二上拉晶体管和第二下拉晶体管的多个NAND门，并且如果至少两个输入信号中的至少一个分别具有低电平，则产生具有高电平的输出信号，其中at 至少一个第一上拉晶体管和第一下拉晶体管和至少两个第二上拉晶体管和第二下拉晶体管堆叠并布置在至少两层上。

3. 发明授权

US07315466B2 Semiconductor memory device and method for arranging and manufacturing the same 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US07315466B2
公开(公告)日：2008-01-01
申请号：US11191496
申请日：2005-07-28
申请人： Gong-Heum Han , Hyou-Youn Nam , Bo-Tak Lim , Han-Byung Park , Soon-Moon Jung , Hoon Lim
发明人： Gong-Heum Han , Hyou-Youn Nam , Bo-Tak Lim , Han-Byung Park , Soon-Moon Jung , Hoon Lim
IPC分类号： G11C11/00
CPC分类号： G11C11/412 , H01L21/8221 , H01L27/0688 , H01L27/105 , H01L27/11 , H01L27/1108 , H01L27/1116
摘要： A semiconductor device and method for arranging and manufacturing the same are disclosed. The semiconductor device includes a plurality of inverters including at least one first pull-up transistor and first pull-down transistor and inverting and outputting an input signal, respectively; and a plurality of NAND gates including at least two second pull-up transistor and second pull-down transistor and generating an output signal having a high level if at least one of at least two input signals has a low level, respectively, wherein the at least one first pull-up transistor and first pull-down transistor and the at least two second pull-up transistor and second pull-down transistor are stacked and arranged on at least two layers.
摘要翻译：公开了一种半导体装置及其制造方法。半导体器件包括多个反相器，包括至少一个第一上拉晶体管和第一下拉晶体管，并分别反相并输出输入信号; 以及包括至少两个第二上拉晶体管和第二下拉晶体管的多个NAND门，并且如果至少两个输入信号中的至少一个分别具有低电平，则产生具有高电平的输出信号，其中at 至少一个第一上拉晶体管和第一下拉晶体管和至少两个第二上拉晶体管和第二下拉晶体管堆叠并布置在至少两层上。

4. 发明授权

US07982221B2 Semiconductor memory device having three dimensional structure 有权
标题翻译：具有三维结构的半导体存储器件
公开(公告)号：US07982221B2
公开(公告)日：2011-07-19
申请号：US12537521
申请日：2009-08-07
申请人： Gong-Heum Han , Hyou-Youn Nam , Bo-Tak Lim , Han-Byung Park , Soon-Moon Jung , Hoon Lim
发明人： Gong-Heum Han , Hyou-Youn Nam , Bo-Tak Lim , Han-Byung Park , Soon-Moon Jung , Hoon Lim
IPC分类号： H01L29/76
CPC分类号： G11C11/412 , H01L21/8221 , H01L27/0688 , H01L27/105 , H01L27/11 , H01L27/1108 , H01L27/1116
摘要： A semiconductor device and method for arranging and manufacturing the same are disclosed. The semiconductor device includes a plurality of inverters including at least one first pull-up transistor and first pull-down transistor and inverting and outputting an input signal, respectively; and a plurality of NAND gates including at least two second pull-up transistor and second pull-down transistor and generating an output signal having a high level if at least one of at least two input signals has a low level, respectively, wherein the at least one first pull-up transistor and first pull-down transistor and the at least two second pull-up transistor and second pull-down transistor are stacked and arranged on at least two layers.
摘要翻译：公开了一种半导体装置及其制造方法。半导体器件包括多个反相器，包括至少一个第一上拉晶体管和第一下拉晶体管，并分别反相并输出输入信号; 以及包括至少两个第二上拉晶体管和第二下拉晶体管的多个NAND门，并且如果至少两个输入信号中的至少一个分别具有低电平，则产生具有高电平的输出信号，其中at 至少一个第一上拉晶体管和第一下拉晶体管和至少两个第二上拉晶体管和第二下拉晶体管堆叠并布置在至少两层上。

5. 发明申请

US20110266623A1 Semiconductor Memory Device Having Three Dimensional Structure 审中-公开
标题翻译：具有三维结构的半导体存储器件
公开(公告)号：US20110266623A1
公开(公告)日：2011-11-03
申请号：US13185184
申请日：2011-07-18
申请人： Gong-Heum Han , Hyou-Youn Nam , Bo-Tak Lim , Han-Byung Park , Soon-Moon Jung , Hoon Lim
发明人： Gong-Heum Han , Hyou-Youn Nam , Bo-Tak Lim , Han-Byung Park , Soon-Moon Jung , Hoon Lim
IPC分类号： H01L27/12
CPC分类号： G11C11/412 , H01L21/8221 , H01L27/0688 , H01L27/105 , H01L27/11 , H01L27/1108 , H01L27/1116
摘要： A semiconductor device and method for arranging and manufacturing the same are disclosed. The semiconductor device includes a plurality of inverters including at least one first pull-up transistor and first pull-down transistor and inverting and outputting an input signal, respectively; and a plurality of NAND gates including at least two second pull-up transistor and second pull-down transistor and generating an output signal having a high level if at least one of at least two input signals has a low level, respectively, wherein the at least one first pull-up transistor and first pull-down transistor and the at least two second pull-up transistor and second pull-down transistor are stacked and arranged on at least two layers.
摘要翻译：公开了一种半导体装置及其制造方法。半导体器件包括多个反相器，包括至少一个第一上拉晶体管和第一下拉晶体管，并分别反相并输出输入信号; 以及包括至少两个第二上拉晶体管和第二下拉晶体管的多个NAND门，并且如果至少两个输入信号中的至少一个分别具有低电平，则产生具有高电平的输出信号，其中at 至少一个第一上拉晶体管和第一下拉晶体管和至少两个第二上拉晶体管和第二下拉晶体管堆叠并布置在至少两层上。

6. 发明申请

US20080089163A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR ARRANGING AND MANUFACTURING THE SAME 有权
标题翻译：半导体存储器件及其制造和制造方法
公开(公告)号：US20080089163A1
公开(公告)日：2008-04-17
申请号：US11953289
申请日：2007-12-10
申请人： Gong-Heum Han , Hyou-Youn Nam , Bo-Tak Lim , Han-Byung Park , Soon-Moon Jung , Hoon Lim
发明人： Gong-Heum Han , Hyou-Youn Nam , Bo-Tak Lim , Han-Byung Park , Soon-Moon Jung , Hoon Lim
IPC分类号： G11C8/10
CPC分类号： G11C11/412 , H01L21/8221 , H01L27/0688 , H01L27/105 , H01L27/11 , H01L27/1108 , H01L27/1116
摘要： A semiconductor device and method for arranging and manufacturing the same are disclosed. The semiconductor device includes a plurality of inverters including at least one first pull-up transistor and first pull-down transistor and inverting and outputting an input signal, respectively; and a plurality of NAND gates including at least two second pull-up transistor and second pull-down transistor and generating an output signal having a high level if at least one of at least two input signals has a low level, respectively, wherein the at least one first pull-up transistor and first pull-down transistor and the at least two second pull-up transistor and second pull-down transistor are stacked and arranged on at least two layers.
摘要翻译：公开了一种半导体装置及其制造方法。半导体器件包括多个反相器，包括至少一个第一上拉晶体管和第一下拉晶体管，并分别反相并输出输入信号; 以及包括至少两个第二上拉晶体管和第二下拉晶体管的多个NAND门，并且如果至少两个输入信号中的至少一个分别具有低电平，则产生具有高电平的输出信号，其中at 至少一个第一上拉晶体管和第一下拉晶体管和至少两个第二上拉晶体管和第二下拉晶体管堆叠并布置在至少两层上。

7. 发明申请

US20060028861A1 Semiconductor memory device and method for arranging and manufacturing the same 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20060028861A1
公开(公告)日：2006-02-09
申请号：US11191496
申请日：2005-07-28
申请人： Gong-Heum Han , Hyou-Youn Nam , Bo-Tak Lim , Han-Byung Park , Soon-Moon Jung , Hoon Lim
发明人： Gong-Heum Han , Hyou-Youn Nam , Bo-Tak Lim , Han-Byung Park , Soon-Moon Jung , Hoon Lim
IPC分类号： G11C11/00
CPC分类号： G11C11/412 , H01L21/8221 , H01L27/0688 , H01L27/105 , H01L27/11 , H01L27/1108 , H01L27/1116
摘要： A semiconductor device and method for arranging and manufacturing the same are disclosed. The semiconductor device includes a plurality of inverters including at least one first pull-up transistor and first pull-down transistor and inverting and outputting an input signal, respectively; and a plurality of NAND gates including at least two second pull-up transistor and second pull-down transistor and generating an output signal having a high level if at least one of at least two input signals has a low level, respectively, wherein the at least one first pull-up transistor and first pull-down transistor and the at least two second pull-up transistor and second pull-down transistor are stacked and arranged on at least two layers.
摘要翻译：公开了一种半导体装置及其制造方法。半导体器件包括多个反相器，包括至少一个第一上拉晶体管和第一下拉晶体管，并分别反相并输出输入信号; 以及包括至少两个第二上拉晶体管和第二下拉晶体管的多个NAND门，并且如果至少两个输入信号中的至少一个分别具有低电平，则产生具有高电平的输出信号，其中at 至少一个第一上拉晶体管和第一下拉晶体管和至少两个第二上拉晶体管和第二下拉晶体管堆叠并布置在至少两层上。

8. 发明申请

US20060157737A1 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US20060157737A1
公开(公告)日：2006-07-20
申请号：US11326159
申请日：2006-01-05
申请人： Bo-Tak Lim , Su-Yeon Kim , Jong-Pil Son , Gong-Heum Han
发明人： Bo-Tak Lim , Su-Yeon Kim , Jong-Pil Son , Gong-Heum Han
IPC分类号： H01L27/10
CPC分类号： H01L27/0207 , H01L27/105 , H01L27/10897 , H01L27/11898
摘要： A semiconductor memory device comprises a cell region including a plurality of unit memory cells, and a peripheral circuit region, the peripheral circuit region including a plurality of peripheral circuit devices for operating the plurality of memory cells and at least one operating capacitor formed adjacent to at least one peripheral circuit device at a pseudo circuit pattern region.
摘要翻译：一种半导体存储器件包括一个包括多个单元存储单元的单元区域和一个外围电路区域，该外围电路区域包括用于操作该多个存储单元的多个外围电路器件以及邻近形成的至少一个工作电容器在伪电路图案区域中的至少一个外围电路器件。

9. 发明授权

US07608880B2 Semiconductor memory device having a peripheral region including operating capacitors 有权
标题翻译：具有包括工作电容器的外围区域的半导体存储器件
公开(公告)号：US07608880B2
公开(公告)日：2009-10-27
申请号：US11326159
申请日：2006-01-05
申请人： Bo-Tak Lim , Su-Yeon Kim , Jong-Pil Son , Gong-Heum Han
发明人： Bo-Tak Lim , Su-Yeon Kim , Jong-Pil Son , Gong-Heum Han
IPC分类号： H01L27/108
CPC分类号： H01L27/0207 , H01L27/105 , H01L27/10897 , H01L27/11898
摘要： A semiconductor memory device comprises a cell region including a plurality of unit memory cells, and a peripheral circuit region, the peripheral circuit region including a plurality of peripheral circuit devices for operating the plurality of memory cells and at least one operating capacitor formed adjacent to at least one peripheral circuit device at a pseudo circuit pattern region.
摘要翻译：一种半导体存储器件包括一个包括多个单元存储单元的单元区域和一个外围电路区域，该外围电路区域包括用于操作该多个存储单元的多个外围电路器件以及邻近形成的至少一个工作电容器在伪电路图案区域中的至少一个外围电路器件。

10. 发明授权

US06870783B2 Mode entrance control circuit and mode entering method in semiconductor memory device 失效
标题翻译：半导体存储器件中的入口控制电路和模式进入方法
公开(公告)号：US06870783B2
公开(公告)日：2005-03-22
申请号：US10661581
申请日：2003-09-15
申请人： Choong-Keun Kwak , Bo-Tak Lim
发明人： Choong-Keun Kwak , Bo-Tak Lim
IPC分类号： G11C5/14 , G11C7/10 , G11C11/4193 , G11C29/46
CPC分类号： G11C7/1045 , G11C29/46
摘要： In a mode entrance control circuit and a mode entering method to stably enter a semiconductor memory device into a predetermined operating mode only when insensitive to a change of a process, temperature, or voltage, etc., and simultaneously satisfying a constant entrance condition, the mode entrance control circuit includes an operation control part for generating an operation enable signal when a first voltage applied through a first pad is over a first determination voltage, a voltage division part for dividing a second voltage applied through a second pad to generate a trimming reference voltage, and a mode entrance signal generating part operated in response to the operation enable signal, for comparing a level of an applied fixed reference voltage with a level of the trimming reference voltage, and for generating a mode entrance enable signal to allow the semiconductor memory device to enter into a predetermined mode.
摘要翻译：在模式入口控制电路和模式输入方法中，只有当对过程，温度或电压等的改变不敏感并且同时满足恒定的入口条件时，才能将半导体存储器件稳定地进入预定的操作模式，模式入口控制电路包括：操作控制部分，用于当通过第一焊盘施加的第一电压超过第一确定电压时产生操作使能信号;分压部分，用于分割通过第二焊盘施加的第二电压，以产生修整参考电压和模式入口信号产生部件，其响应于所述操作使能信号而被操作，用于将所施加的固定参考电压的电平与所述修整参考电压的电平进行比较，并且用于产生模式入口使能信号以允许所述半导体存储器设备进入预定模式。

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