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    • 1. 发明申请
    • Voltage regulator with adjustable output impedance
    • 稳压器,输出阻抗可调
    • US20050035746A1
    • 2005-02-17
    • US10804860
    • 2004-03-19
    • Giuseppe BernacchiaGiorgio ChiozziMaurizio Galvano
    • Giuseppe BernacchiaGiorgio ChiozziMaurizio Galvano
    • G05F1/40H02M3/158
    • H02M3/1588H02M2001/0009Y02B70/1466
    • The invention relates to a voltage regulator having an output terminal (AK) for the provision of an output voltage and connection of a load, an output capacitor (20) connected to the output terminal and having an equivalent series resistance (ESR), a converter unit (10) having supply voltage terminals for the application of a supply voltage (Vcc), an output coupled to the output terminal (AK), a feedback signal input for feeding in a feedback signal (Vfb) dependent on the output voltage, a reference signal input for feeding in a reference signal (Vref), and a comparator unit (TA3), which provides a differential signal (Iea) from the reference signal (Vref) and the feedback signal (Vfb), in which case the converter unit (10) provides an output current (Iout), the mean value of which is proportional to the differential signal (Iea), the proportionality factor between this difference and the output current (Iout) being set by means of a control signal at a control input of the converter unit (10) in such a way that it is proportional to the reciprocal of the equivalent series resistance (ESR) of the output capacitor.
    • 本发明涉及一种具有用于提供输出电压和负载连接的输出端子(AK),连接到输出端子并具有等效串联电阻(ESR)的输出电容器(20)的电压调节器,转换器 具有用于施加电源电压(Vcc)的电源电压端子的单元(10),耦合到输出端子(AK)的输出端,用于馈送取决于输出电压的反馈信号(Vfb)的反馈信号输入端 用于馈送参考信号(Vref)的参考信号输入以及从参考信号(Vref)和反馈信号(Vfb)提供差分信号(Iea)的比较器单元(TA3),在这种情况下,转换器单元 (10)提供其平均值与差分信号(Iea)成比例的输出电流(Iout),该差值与输出电流(Iout)之间的比例因子通过控制下的控制信号来设定 转换器的输入u nit(10),使其与输出电容器的等效串联电阻(ESR)的倒数成正比。
    • 2. 发明授权
    • Voltage regulator with adjustable output impedance
    • 稳压器,输出阻抗可调
    • US07023191B2
    • 2006-04-04
    • US10804860
    • 2004-03-19
    • Giuseppe BernacchiaGiorgio ChiozziMaurizio Galvano
    • Giuseppe BernacchiaGiorgio ChiozziMaurizio Galvano
    • G05F1/40
    • H02M3/1588H02M2001/0009Y02B70/1466
    • The invention relates to a voltage regulator having an output terminal (AK) for the provision of an output voltage and connection of a load, an output capacitor (20) connected to the output terminal and having an equivalent series resistance (ESR), a converter unit (10) having supply voltage terminals for the application of a supply voltage (Vcc), an output coupled to the output terminal (AK), a feedback signal input for feeding in a feedback signal (Vfb) dependent on the output voltage, a reference signal input for feeding in a reference signal (Vref), and a comparator unit (TA3), which provides a differential signal (Iea) from the reference signal (Vref) and the feedback signal (Vfb), in which case the converter unit (10) provides an output current (Iout), the mean value of which is proportional to the differential signal (Iea), the proportionality factor between this difference and the output current (Iout) being set by means of a control signal at a control input of the converter unit (10) in such a way that it is proportional to the reciprocal of the equivalent series resistance (ESR) of the output capacitor.
    • 本发明涉及一种具有用于提供输出电压和负载连接的输出端子(AK),连接到输出端子并具有等效串联电阻(ESR)的输出电容器(20)的电压调节器,转换器 具有用于施加电源电压(Vcc)的电源电压端子的单元(10),耦合到输出端子(AK)的输出端,用于馈送取决于输出电压的反馈信号(Vfb)的反馈信号输入端 用于馈送参考信号(Vref)的参考信号输入和从参考信号(Vref)和反馈信号(Vfb)提供差分信号(Iea)的比较器单元(TA 3),在这种情况下转换器 单元(10)提供其平均值与差分信号(Iea)成比例的输出电流(Iout),该差值与输出电流(Iout)之间的比例因子通过在 控制输入​​的控制 转换器单元(10)以与输出电容器的等效串联电阻(ESR)的倒数成比例的方式。
    • 3. 发明申请
    • Discontinuous Conduction Mode Control Circuit and Method for Synchronous Converter
    • 不连续导通模式控制电路和同步转换器的方法
    • US20090323375A1
    • 2009-12-31
    • US12164954
    • 2008-06-30
    • Maurizio GalvanoGiuseppe BernacchiaGiovanni Capodivacca
    • Maurizio GalvanoGiuseppe BernacchiaGiovanni Capodivacca
    • H02M3/335
    • H02M3/156H02M3/3376
    • Circuit and method for controlling a synchronous power converter in discontinuous conduction mode with increased efficiency is disclosed. Circuitry is provided outputting gating signals to a high side driver and a synchronous rectifier responsive to a pulse width modulated input signal, an inhibit circuit for inhibiting the gating signal to the synchronous rectifier upon detection of a zero crossing condition; a comparator receiving a measured circuit value from the synchronous converter and a reference value and outputting a zero crossing condition; and a duty cycle observer circuit for determining the average duty cycle of the pulse width modulated input signal and for varying the reference value. A method is disclosed determining if the average duty cycle in the pulse width modulated input signal is increasing in response to varying a reference value, and inhibiting a synchronous rectifier control signal when the comparator indicates a zero crossing condition.
    • 公开了用于以提高效率控制不连续导通模式的同步功率转换器的电路和方法。 提供电路,其响应于脉宽调制输入信号向高侧驱动器和同步整流器输出门控信号;禁止电路,用于在检测到过零状态时禁止同步整流器的选通信号; 比较器,从同步转换器接收测量电路值和参考值,并输出过零状态; 以及用于确定脉宽调制输入信号的平均占空比并用于改变参考值的占空比观察器电路。 公开了一种确定脉冲宽度调制输入信号中的平均占空比是否响应于改变参考值而增加的方法,以及当比较器指示过零状态时禁止同步整流器控制信号。
    • 5. 发明授权
    • Method for driving a transistor half-bridge
    • 驱动晶体管半桥的方法
    • US07583111B2
    • 2009-09-01
    • US11825323
    • 2007-07-05
    • Maurizio Galvano
    • Maurizio Galvano
    • H03B1/00
    • H02M1/38
    • A method drives a transistor half-bridge. The method includes measuring a delay time between an edge of an input signal and an corresponding edge of a phase signal, and saving the delay time as a saved delay time value. The phase signal is the output of the transistor half-bridge. In the method, the following steps are repeated until the saved delay time value differs from the delay time by more than a given threshold: decrementing the delay-value of a programmable delay circuit and the saved delay time value by a given decrement, the programmable delay circuit coupled to a control terminal of a first transistor of the half-bridge, and measuring the delay time between an edge of the input signal and an corresponding edge of the phase signal.
    • 一种驱动晶体管半桥的方法。 该方法包括测量输入信号的边沿和相位信号的相应边缘之间的延迟时间,并将延迟时间保存为保存的延迟时间值。 相位信号是晶体管半桥的输出。 在该方法中,重复以下步骤,直到保存的延迟时间值与延迟时间不同于给定阈值:递减可编程延迟电路的延迟值和保存的延迟时间值给定的减量,可编程 延迟电路耦合到半桥的第一晶体管的控制端,并测量输入信号的边沿与相位信号的相应边沿之间的延迟时间。
    • 8. 发明申请
    • Method for driving a transistor half-bridge
    • 驱动晶体管半桥的方法
    • US20080246518A1
    • 2008-10-09
    • US11825323
    • 2007-07-05
    • Maurizio Galvano
    • Maurizio Galvano
    • H03K3/017
    • H02M1/38
    • A method drives a transistor half-bridge. The method includes measuring a delay time between an edge of an input signal and an corresponding edge of a phase signal, and saving the delay time as a saved delay time value. The phase signal is the output of the transistor half-bridge. In the method, the following steps are repeated until the saved delay time value differs from the delay time by more than a given threshold: decrementing the delay-value of a programmable delay circuit and the saved delay time value by a given decrement, the programmable delay circuit coupled to a control terminal of a first transistor of the half-bridge, and measuring the delay time between an edge of the input signal and an corresponding edge of the phase signal.
    • 一种驱动晶体管半桥的方法。 该方法包括测量输入信号的边沿和相位信号的相应边缘之间的延迟时间,并将延迟时间保存为保存的延迟时间值。 相位信号是晶体管半桥的输出。 在该方法中,重复以下步骤,直到保存的延迟时间值与延迟时间不同于给定阈值:递减可编程延迟电路的延迟值和保存的延迟时间值减去给定的递减,可编程 延迟电路耦合到半桥的第一晶体管的控制端,并测量输入信号的边沿与相位信号的相应边沿之间的延迟时间。
    • 9. 发明授权
    • Drive circuit for two switching converter stages in a voltage converter
    • 电压转换器中两个开关转换器级的驱动电路
    • US07342385B2
    • 2008-03-11
    • US11336643
    • 2006-01-19
    • Giovanni CapodivaccaMaurizio Galvano
    • Giovanni CapodivaccaMaurizio Galvano
    • G05F1/40
    • H02M3/1584
    • A drive circuit is disclosed including a first feedback circuit designed to generate a first feedback signal from a first voltage to be controlled and a first reference voltage. The drive circuit further includes a signal converter designed to generate a second feedback signal from the first feedback signal such that the difference between the first feedback signal and a first amplitude value of a periodic signal approximately matches the difference between the second feedback signal and a second amplitude value of the periodic signal. The drive circuit also includes a first pulse width modulator which receives the first feedback signal and the periodic signal and generates the first pulse width-modulated signal. In addition the drive circuit includes a second pulse width modulator which receives the second feedback signal and the periodic signal and generates the second pulse width-modulated signal.
    • 公开了一种驱动电路,其包括设计成从要控制的第一电压和第一参考电压产生第一反馈信号的第一反馈电路。 驱动电路还包括信号转换器,被设计为从第一反馈信号产生第二反馈信号,使得第一反馈信号与周期信号的第一幅度值之间的差近似匹配第二反馈信号与第二反馈信号之间的差 周期信号的振幅值。 驱动电路还包括第一脉冲宽度调制器,其接收第一反馈信号和周期信号并产生第一脉冲宽度调制信号。 此外,驱动电路包括接收第二反馈信号和周期信号并产生第二脉冲宽度调制信号的第二脉冲宽度调制器。