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1. 发明申请

US20130034948A1 Method of Manufacturing a Semiconductor Device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20130034948A1
公开(公告)日：2013-02-07
申请号：US13204352
申请日：2011-08-05
申请人： Gin-Chen Huang , Yi-An Lin , Ching-Hong Jiang , Neng-Kuo Chen , Sey-Ping Sun , Clement Hsingjen Wann
发明人： Gin-Chen Huang , Yi-An Lin , Ching-Hong Jiang , Neng-Kuo Chen , Sey-Ping Sun , Clement Hsingjen Wann
IPC分类号： H01L21/762
CPC分类号： H01L21/76224 , H01L21/3081 , H01L21/31053 , H01L21/31055
摘要： A method for fabricating a semiconductor device is disclosed. An exemplary method includes a providing substrate. A dielectric layer is formed over the semiconductor substrate and a stop layer is formed over the dielectric layer. The stop layer and the dielectric layer comprise a different material. The method further includes forming a patterned hard mask layer over the stop layer and etching the semiconductor substrate through the patterned hard mask layer to form a plurality of trenches. The method also includes depositing an isolation material on the semiconductor substrate and substantially filling the plurality of trenches. Thereafter, performing a CMP process on the semiconductor substrate, wherein the CMP process stops on the stop layer.
摘要翻译：公开了一种制造半导体器件的方法。一种示例性方法包括提供衬底。在半导体衬底上形成电介质层，并在电介质层上形成阻挡层。阻挡层和电介质层包括不同的材料。该方法还包括在停止层上形成图案化的硬掩模层，并通过图案化的硬掩模层蚀刻半导体衬底以形成多个沟槽。该方法还包括在半导体衬底上沉积隔离材料并基本上填充多个沟槽。此后，在半导体衬底上执行CMP处理，其中CMP处理在停止层上停止。

2. 发明授权

US08853052B2 Method of manufacturing a semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08853052B2
公开(公告)日：2014-10-07
申请号：US13204352
申请日：2011-08-05
申请人： Gin-Chen Huang , Yi-An Lin , Ching-Hong Jiang , Neng-Kuo Chen , Sey-Ping Sun , Clement Hsingjen Wann
发明人： Gin-Chen Huang , Yi-An Lin , Ching-Hong Jiang , Neng-Kuo Chen , Sey-Ping Sun , Clement Hsingjen Wann
IPC分类号： H01L21/76 , H01L29/00 , H01L21/308 , H01L21/3105 , H01L21/762
CPC分类号： H01L21/76224 , H01L21/3081 , H01L21/31053 , H01L21/31055
摘要： A method for fabricating a semiconductor device is disclosed. An exemplary method includes a providing substrate. A dielectric layer is formed over the semiconductor substrate and a stop layer is formed over the dielectric layer. The stop layer and the dielectric layer comprise a different material. The method further includes forming a patterned hard mask layer over the stop layer and etching the semiconductor substrate through the patterned hard mask layer to form a plurality of trenches. The method also includes depositing an isolation material on the semiconductor substrate and substantially filling the plurality of trenches. Thereafter, performing a CMP process on the semiconductor substrate, wherein the CMP process stops on the stop layer.
摘要翻译：公开了一种制造半导体器件的方法。一种示例性方法包括提供衬底。在半导体衬底上形成电介质层，并在电介质层上形成阻挡层。阻挡层和电介质层包括不同的材料。该方法还包括在停止层上形成图案化的硬掩模层，并通过图案化的硬掩模层蚀刻半导体衬底以形成多个沟槽。该方法还包括在半导体衬底上沉积隔离材料并基本上填充多个沟槽。此后，在半导体衬底上执行CMP处理，其中CMP处理在停止层上停止。

3. 发明申请

US20130043512A1 Semiconductor Device Manufacturing Methods and Methods of Forming Insulating Material Layers 有权
公开(公告)号：US20130043512A1
公开(公告)日：2013-02-21
申请号：US13212834
申请日：2011-08-18
申请人： Gin-Chen Huang , Tsai-Fu Hsiao , Ching-Hong Jiang , Neng-Kuo Chen , Hongfa Luan , Sey-Ping Sun , Clement Hsingjen Wann
发明人： Gin-Chen Huang , Tsai-Fu Hsiao , Ching-Hong Jiang , Neng-Kuo Chen , Hongfa Luan , Sey-Ping Sun , Clement Hsingjen Wann
IPC分类号： H01L21/31 , H01L21/28 , H01L29/78
CPC分类号： H01L21/02274 , H01L21/02164 , H01L21/022 , H01L21/0228 , H01L21/02332 , H01L21/324 , H01L29/66795
摘要： Semiconductor device manufacturing methods and methods of forming insulating material layers are disclosed. In one embodiment, a method of forming a composite insulating material layer of a semiconductor device includes providing a workpiece and forming a first sub-layer of the insulating material layer over the workpiece using a first plasma power level. A second sub-layer of the insulating material layer is formed over the first sub-layer of the insulating material layer using a second plasma power level, and the workpiece is annealed.

4. 发明授权

US09006802B2 Semiconductor device manufacturing methods and methods of forming insulating material layers 有权
标题翻译：形成绝缘材料层的半导体器件制造方法和方法
公开(公告)号：US09006802B2
公开(公告)日：2015-04-14
申请号：US13212834
申请日：2011-08-18
申请人： Gin-Chen Huang , Tsai-Fu Hsiao , Ching-Hong Jiang , Neng-Kuo Chen , Hongfa Luan , Sey-Ping Sun , Clement Hsingjen Wann
发明人： Gin-Chen Huang , Tsai-Fu Hsiao , Ching-Hong Jiang , Neng-Kuo Chen , Hongfa Luan , Sey-Ping Sun , Clement Hsingjen Wann
IPC分类号： H01L29/78 , H01L21/02 , H01L29/66
CPC分类号： H01L21/02274 , H01L21/02164 , H01L21/022 , H01L21/0228 , H01L21/02332 , H01L21/324 , H01L29/66795
摘要： Semiconductor device manufacturing methods and methods of forming insulating material layers are disclosed. In one embodiment, a method of forming a composite insulating material layer of a semiconductor device includes providing a workpiece and forming a first sub-layer of the insulating material layer over the workpiece using a first plasma power level. A second sub-layer of the insulating material layer is formed over the first sub-layer of the insulating material layer using a second plasma power level, and the workpiece is annealed.
摘要翻译：公开了形成绝缘材料层的半导体器件制造方法和方法。在一个实施例中，形成半导体器件的复合绝缘材料层的方法包括提供工件并使用第一等离子体功率电平在工件上形成绝缘材料层的第一子层。使用第二等离子体功率电平在绝缘材料层的第一子层上形成绝缘材料层的第二子层，并且将工件退火。

5. 发明申请

US20130113026A1 FIN FIELD EFFECT TRANSISTOR GATE OXIDE 有权
标题翻译： FIN场效应晶体管栅氧化物
公开(公告)号：US20130113026A1
公开(公告)日：2013-05-09
申请号：US13288407
申请日：2011-11-03
申请人： Gin-Chen Huang , Neng-Kuo Chen , Clement Hsingjen Wann
发明人： Gin-Chen Huang , Neng-Kuo Chen , Clement Hsingjen Wann
IPC分类号： H01L29/772 , H01L21/28
CPC分类号： H01L29/66795 , H01L29/785
摘要： The present disclosure provides for methods of fabricating a semiconductor device and such a device. A method includes providing a substrate including at least two isolation features, forming a fin substrate above the substrate and between the at least two isolation features, forming a silicon liner over the fin substrate, and oxidizing the silicon liner to form a silicon oxide liner over the fin substrate.
摘要翻译：本公开提供了制造半导体器件和这种器件的方法。一种方法包括提供包括至少两个隔离特征的基底，在基底之上和在至少两个隔离特征之间形成翅片基底，在翅片衬底上形成硅衬垫，并氧化硅衬垫以形成氧化硅衬垫翅片基板。

6. 发明授权

US09105661B2 Fin field effect transistor gate oxide 有权
标题翻译： Fin场效应晶体管栅极氧化物
公开(公告)号：US09105661B2
公开(公告)日：2015-08-11
申请号：US13288407
申请日：2011-11-03
申请人： Gin-Chen Huang , Neng-Kuo Chen , Hsingjen Wann
发明人： Gin-Chen Huang , Neng-Kuo Chen , Hsingjen Wann
IPC分类号： H01L21/00 , H01L29/66 , H01L29/78
CPC分类号： H01L29/66795 , H01L29/785
摘要： The present disclosure provides for methods of fabricating a semiconductor device and such a device. A method includes providing a substrate including at least two isolation features, forming a fin substrate above the substrate and between the at least two isolation features, forming a silicon liner over the fin substrate, and oxidizing the silicon liner to form a silicon oxide liner over the fin substrate.
摘要翻译：本公开提供了制造半导体器件和这种器件的方法。一种方法包括提供包括至少两个隔离特征的基底，在基底之上和在至少两个隔离特征之间形成翅片基底，在翅片衬底上形成硅衬垫，并氧化硅衬垫以形成氧化硅衬垫翅片基板。

7. 发明授权

US08614152B2 Gate structure and a method for forming the same 有权
标题翻译：栅结构及其形成方法
公开(公告)号：US08614152B2
公开(公告)日：2013-12-24
申请号：US13115186
申请日：2011-05-25
申请人： Chien-Liang Lin , Gin-Chen Huang , Ying-Wei Yen , Yu-Ren Wang
发明人： Chien-Liang Lin , Gin-Chen Huang , Ying-Wei Yen , Yu-Ren Wang
IPC分类号： H01L21/31
CPC分类号： H01L29/518 , B82Y40/00 , H01L21/28035 , H01L21/28176 , H01L21/28202 , H01L29/4925
摘要： A method for forming a gate structure includes the following steps. A substrate is provided. A silicon oxide layer is formed on the substrate. A decoupled plasma-nitridation process is applied to the silicon oxide layer so as to form a silicon oxynitride layer. A first polysilicon layer is formed on the silicon oxynitride layer. A thermal process is applied to the silicon oxynitride layer having the first polysilicon layer. After the thermal process, a second polysilicon layer is formed on the first polysilicon layer. The first polysilicon layer can protect the gate dielectric layer during the thermal process. The nitrogen atoms inside the gate dielectric layer do not lose out of the gate dielectric layer. Thus, the out-gassing phenomenon can be avoided, and a dielectric constant of the gate dielectric layer can not be changed, thereby increasing the reliability of the gate structure.
摘要翻译：一种形成栅极结构的方法包括以下步骤。提供基板。在基板上形成氧化硅层。对氧化硅层施加去耦等离子体氮化处理以形成氮氧化硅层。在氮氧化硅层上形成第一多晶硅层。对具有第一多晶硅层的氧氮化硅层施加热处理。在热处理之后，在第一多晶硅层上形成第二多晶硅层。第一多晶硅层可以在热处理期间保护栅极介电层。栅极电介质层内的氮原子不会从栅介质层中流出。因此，可以避免排气现象，并且不能改变栅极电介质层的介电常数，从而增加栅极结构的可靠性。

8. 发明申请

US20120309171A1 METHOD FOR FABRICATING SEMICONDUCTOR DEVICE 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：US20120309171A1
公开(公告)日：2012-12-06
申请号：US13118473
申请日：2011-05-30
申请人： Tsuo-Wen Lu , Wen-Yi Teng , Yu-Ren Wang , Gin-Chen Huang , Chien-Liang Lin , Shao-Wei Wang , Ying-Wei Yen , Ya-Chi Cheng , Shu-Yen Chan , Chan-Lon Yang
发明人： Tsuo-Wen Lu , Wen-Yi Teng , Yu-Ren Wang , Gin-Chen Huang , Chien-Liang Lin , Shao-Wei Wang , Ying-Wei Yen , Ya-Chi Cheng , Shu-Yen Chan , Chan-Lon Yang
IPC分类号： H01L21/20
CPC分类号： H01L29/6656 , H01L29/165 , H01L29/66636 , H01L29/7834 , H01L29/7848
摘要： A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate, wherein the substrate comprises a gate structure thereon; forming a film stack on the substrate and covering the gate structure, wherein the film stack comprises at least an oxide layer and a nitride layer; removing a portion of the film stack for forming recesses adjacent to two sides of the gate structure and a disposable spacer on the sidewall of the gate structure; and filling the recesses with a material comprising silicon atoms for forming a faceted material layer.
摘要翻译：公开了半导体器件的制造方法。该方法包括以下步骤：提供衬底，其中衬底包括其上的栅极结构; 在所述衬底上形成膜叠层并覆盖所述栅极结构，其中所述膜堆叠至少包括氧化物层和氮化物层; 移除所述薄膜叠层的一部分以形成邻近所述栅极结构的两侧的凹槽和所述栅极结构侧壁上的一次性间隔物; 并用包含硅原子的材料填充凹部，以形成刻面材料层。

9. 发明申请

US20120228723A1 GATE STRUCTURE AND METHOD FOR FABRICATING THE SAME 有权
标题翻译：盖结构及其制造方法
公开(公告)号：US20120228723A1
公开(公告)日：2012-09-13
申请号：US13045291
申请日：2011-03-10
申请人： Shao-Wei Wang , Gin-Chen Huang , Tsuo-Wen Lu , Chien-Liang Lin , Yu-Ren Wang
发明人： Shao-Wei Wang , Gin-Chen Huang , Tsuo-Wen Lu , Chien-Liang Lin , Yu-Ren Wang
IPC分类号： H01L29/772 , H01L21/28
CPC分类号： H01L29/513 , H01L21/28185 , H01L21/28202 , H01L29/518
摘要： A gate structure and a method for fabricating the same are described. A substrate is provided, and a gate dielectric layer is formed on the substrate. The formation of the gate dielectric layer includes depositing a silicon nitride layer on the substrate by simultaneously introducing a nitrogen-containing gas and a silicon-containing gas. A gate is formed on the gate dielectric layer, so as to form the gate structure.
摘要翻译：对栅极结构及其制造方法进行说明。提供衬底，并且在衬底上形成栅极电介质层。栅电介质层的形成包括通过同时引入含氮气体和含硅气体在衬底上沉积氮化硅层。栅极形成在栅极介电层上，以形成栅极结构。

10. 发明申请

US20120299124A1 GATE STRUCTURE AND A METHOD FOR FORMING THE SAME 有权
标题翻译：门结构及其形成方法
公开(公告)号：US20120299124A1
公开(公告)日：2012-11-29
申请号：US13115186
申请日：2011-05-25
申请人： Chien-Liang LIN , Gin-Chen Huang , Ying-Wei Yen , Yu-Ren Wang
发明人： Chien-Liang LIN , Gin-Chen Huang , Ying-Wei Yen , Yu-Ren Wang
IPC分类号： H01L29/51 , H01L21/3205 , B82Y40/00 , B82Y99/00
CPC分类号： H01L29/518 , B82Y40/00 , H01L21/28035 , H01L21/28176 , H01L21/28202 , H01L29/4925
摘要： A method for forming a gate structure includes the following steps. A substrate is provided. A silicon oxide layer is formed on the substrate. A decoupled plasma-nitridation process is applied to the silicon oxide layer so as to form a silicon oxynitride layer. A first polysilicon layer is formed on the silicon oxynitride layer. A thermal process is applied to the silicon oxynitride layer having the first polysilicon layer. After the thermal process, a second polysilicon layer is formed on the first polysilicon layer. The first polysilicon layer can protect the gate dielectric layer during the thermal process. The nitrogen atoms inside the gate dielectric layer do not lose out of the gate dielectric layer. Thus, the out-gassing phenomenon can be avoided, and a dielectric constant of the gate dielectric layer can not be changed, thereby increasing the reliability of the gate structure.
摘要翻译：一种形成栅极结构的方法包括以下步骤。提供基板。在基板上形成氧化硅层。对氧化硅层施加去耦等离子体氮化处理以形成氮氧化硅层。在氮氧化硅层上形成第一多晶硅层。对具有第一多晶硅层的氧氮化硅层施加热处理。在热处理之后，在第一多晶硅层上形成第二多晶硅层。第一多晶硅层可以在热处理期间保护栅极介电层。栅极电介质层内的氮原子不会从栅介质层中流出。因此，可以避免排气现象，并且不能改变栅极电介质层的介电常数，从而增加栅极结构的可靠性。

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