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1. 发明授权

US06611477B1 Built-in self test using pulse generators 有权
标题翻译：使用脉冲发生器内置自检
公开(公告)号：US06611477B1
公开(公告)日：2003-08-26
申请号：US10132419
申请日：2002-04-24
申请人： Gil A. Speyer , David L. Ferguson , Daniel Y. Chung , Robert D. Patrie , Robert W. Wells , Robert O. Conn
发明人： Gil A. Speyer , David L. Ferguson , Daniel Y. Chung , Robert D. Patrie , Robert W. Wells , Robert O. Conn
IPC分类号： G04F800
CPC分类号： G01R31/3016 , G01R27/04 , G01R31/2853 , G01R31/2882 , G01R31/31725 , G01R31/318516
摘要： A circuit measures the signal propagation delay through a selected test circuit. The test circuit is provided with a feedback path so that the test circuit and feedback path together form a free-running oscillator. The oscillator then automatically provides its own test signal that includes alternating rising and falling signal transitions on the test-circuit input node. A phase discriminator samples the output of the oscillator and accumulates data representing the signal propagation delay of either rising or falling signal transitions propagating through the test circuit. The worst-case delay associated with the test circuit can then be expressed as the longer of the two. Knowing the precise worst-case delay allows IC A designers to minimize the guard band and consequently guarantee higher speed performance.
摘要翻译：电路通过选定的测试电路测量信号传播延迟。测试电路设置有反馈路径，使得测试电路和反馈路径一起形成自由振荡的振荡器。然后振荡器自动提供自己的测试信号，包括在测试电路输入节点上交替的上升和下降信号转换。相位鉴别器对振荡器的输出进行采样，并累加表示通过测试电路传播的上升或下降信号转换的信号传播延迟的数据。然后，与测试电路相关的最差情况延迟可以表示为两者中较长的时间。了解精确的最坏情况延迟允许IC A设计者将保护带最小化，从而保证更高的速度性能。

2. 发明授权

US06466520B1 Built-in AC self test using pulse generators 有权
标题翻译：使用脉冲发生器内置AC自检
公开(公告)号：US06466520B1
公开(公告)日：2002-10-15
申请号：US09244753
申请日：1999-02-05
申请人： Gil A. Speyer , David L. Ferguson , Daniel Y. Chung , Robert D. Patrie , Robert W. Wells , Robert O. Conn
发明人： Gil A. Speyer , David L. Ferguson , Daniel Y. Chung , Robert D. Patrie , Robert W. Wells , Robert O. Conn
IPC分类号： G04F800
CPC分类号： G01R31/3016 , G01R27/04 , G01R31/2853 , G01R31/2882 , G01R31/31725 , G01R31/318516
摘要： A circuit measures the signal propagation delay through a selected test circuit. The test circuit is provided with a feedback path so that the test circuit and feedback path together form a free-running oscillator. The oscillator then automatically provides its own test signal that includes alternating rising and falling signal transitions on the test-circuit input node. A phase discriminator samples the output of the oscillator and accumulates data representing the signal propagation delay of either rising or falling signal transitions propagating through the test circuit. The worst-case delay associated with the test circuit can then be expressed as the longer of the two. Knowing the precise worst-case delay allows IC designers to minimize the guard band and consequently guarantee higher speed performance.
摘要翻译：电路通过选定的测试电路测量信号传播延迟。测试电路设置有反馈路径，使得测试电路和反馈路径一起形成自由振荡的振荡器。然后振荡器自动提供自己的测试信号，包括在测试电路输入节点上交替的上升和下降信号转换。相位鉴别器对振荡器的输出进行采样，并累加表示通过测试电路传播的上升或下降信号转换的信号传播延迟的数据。与测试电路相关的最坏情况延迟可以表示为两者中较长的时间。了解精确的最坏情况延迟允许IC设计者将保护带最小化，从而保证更高的速度性能。

3. 发明授权

US06219305B1 Method and system for measuring signal propagation delays using ring oscillators 失效
标题翻译：使用环形振荡器测量信号传播延迟的方法和系统
公开(公告)号：US06219305B1
公开(公告)日：2001-04-17
申请号：US09114369
申请日：1998-07-14
申请人： Robert D. Patrie , Robert W. Wells , Steven P. Young , Christopher H. Kingsley , Daniel Chung , Robert O. Conn
发明人： Robert D. Patrie , Robert W. Wells , Steven P. Young , Christopher H. Kingsley , Daniel Chung , Robert O. Conn
IPC分类号： G04F800
CPC分类号： G01R27/04 , G01R31/2853 , G01R31/2882 , G01R31/3016 , G01R31/31725 , G01R31/318516
摘要： A circuit measures the signal propagation delay through a selected test circuit. The test circuit is provided with an inverting feedback path so that the test circuit and feedback path together form a free-running oscillator. The oscillator then automatically provides its own test signal that includes alternating rising and falling signal transitions on the test-circuit input node. These signal transitions are counted over a predetermined time period to establish the average period of the oscillator. Finally, the average period of the oscillator is related to the average signal propagation delay through the test circuit. One embodiment of the invention includes a phase discriminator that samples the output of the oscillator and accumulates data representing the duty cycle of that signal. The duty cycle can then be combined with the average period of the test signal to determine, separately, the delays associated with falling and rising edges propagating through the test circuit.
摘要翻译：电路通过选定的测试电路测量信号传播延迟。测试电路设置有反相反馈路径，使得测试电路和反馈路径一起形成自由振荡的振荡器。然后振荡器自动提供自己的测试信号，包括在测试电路输入节点上交替的上升和下降信号转换。这些信号转换在预定的时间周期内进行计数以建立振荡器的平均周期。最后，振荡器的平均周期与通过测试电路的平均信号传播延迟有关。本发明的一个实施例包括相位鉴别器，其对振荡器的输出进行采样并累加表示该信号的占空比的数据。然后可以将占空比与测试信号的平均周期组合，以分别确定与通过测试电路传播的下降沿和上升沿相关联的延迟。

4. 发明授权

US6069849A Method and system for measuring signal propagation delays using the duty cycle of a ring oscillator 失效
标题翻译：使用环形振荡器的占空比测量信号传播延迟的方法和系统
公开(公告)号：US6069849A
公开(公告)日：2000-05-30
申请号：US115138
申请日：1998-07-14
申请人： Christopher H. Kingsley , Robert D. Patrie , Robert W. Wells , Robert O. Conn
发明人： Christopher H. Kingsley , Robert D. Patrie , Robert W. Wells , Robert O. Conn
IPC分类号： G01R27/04 , G01R31/28 , G01R31/30 , G01R31/317 , G01R31/3185 , G04F8/00 , G01R15/12
CPC分类号： G01R27/04 , G01R31/2853 , G01R31/2882 , G01R31/3016 , G01R31/31725 , G01R31/318516
摘要： A circuit measures the signal propagation delay through a selected test circuit. The test circuit is provided with a feedback path so that the test circuit and feedback path together form a free-running oscillator. The oscillator then automatically provides its own test signal that includes alternating rising and falling signal transitions on the test-circuit input node. These signal transitions are counted over a predetermined time period to establish the average period of the oscillator. Finally, the average period of the oscillator is related to the average signal propagation delay through the test circuit. A phase discriminator samples the output of the oscillator and accumulates data representing the duty cycle of that signal. The duty cycle can then be combined with the average period of the test signal to determine, separately, the delays associated with falling and rising edges propagating through the test circuit.
摘要翻译：电路通过选定的测试电路测量信号传播延迟。测试电路设置有反馈路径，使得测试电路和反馈路径一起形成自由振荡的振荡器。然后振荡器自动提供自己的测试信号，包括在测试电路输入节点上交替的上升和下降信号转换。这些信号转换在预定的时间周期内进行计数以建立振荡器的平均周期。最后，振荡器的平均周期与通过测试电路的平均信号传播延迟有关。相位鉴别器对振荡器的输出采样，并累加表示该信号占空比的数据。然后可以将占空比与测试信号的平均周期组合，以分别确定与通过测试电路传播的下降沿和上升沿相关联的延迟。

5. 发明授权

US06356514B1 Built-in self test method for measuring clock to out delays 有权
标题翻译：内置自检方法，用于测量时钟延迟
公开(公告)号：US06356514B1
公开(公告)日：2002-03-12
申请号：US09816712
申请日：2001-03-23
申请人： Robert W. Wells , Robert D. Patrie , Robert O. Conn
发明人： Robert W. Wells , Robert D. Patrie , Robert O. Conn
IPC分类号： G04F800
CPC分类号： G01R31/3016 , G01R27/04 , G01R31/2853 , G01R31/2882 , G01R31/31725 , G01R31/318516 , G01R31/31937
摘要： A circuit measures the signal propagation delay through a selected test circuit. The test circuit is provided with a feedback path so that the test circuit and feedback path together form a free-running oscillator. The oscillator then automatically provides its own test signal that includes alternating rising and falling signal transitions on the test-circuit input node. These signal transitions are counted over a predetermined time period to establish the period of the oscillator. The period of the oscillator is then related to the average signal propagation delay through the test circuit. The invention can be applied to synchronous components that might fail to oscillate by connecting the asynchronous set or clear terminal to the output terminal so that the oscillator oscillates at a frequency determined by the clock-to-out delay of those components. The configuration can thus be used to characterize synchronous and asynchronous components to provide data for predicting the timing behavior of circuits that include those or similar components.
摘要翻译：电路通过选定的测试电路测量信号传播延迟。测试电路设置有反馈路径，使得测试电路和反馈路径一起形成自由振荡的振荡器。然后振荡器自动提供自己的测试信号，包括在测试电路输入节点上交替的上升和下降信号转换。这些信号转换在预定的时间周期内进行计数，以建立振荡器的周期。然后振荡器的周期与通过测试电路的平均信号传播延迟相关。本发明可以应用于通过将异步设置或清除端子连接到输出端子而可能无法振荡的同步部件，使得振荡器以由那些部件的时钟到输出延迟确定的频率振荡。因此，该配置可以用于表征同步和异步组件，以提供用于预测包括那些或类似组件的电路的定时行为的数据。

6. 发明授权

US06233205B1 Built-in self test method for measuring clock to out delays 失效
标题翻译：内置自检方法，用于测量时钟延迟
公开(公告)号：US06233205B1
公开(公告)日：2001-05-15
申请号：US09115204
申请日：1998-07-14
申请人： Robert W. Wells , Robert D. Patrie , Robert O. Conn
发明人： Robert W. Wells , Robert D. Patrie , Robert O. Conn
IPC分类号： G04F800
CPC分类号： G01R31/3016 , G01R27/04 , G01R31/2853 , G01R31/2882 , G01R31/31725 , G01R31/318516 , G01R31/31937
摘要： A circuit measures the signal propagation delay through a selected test circuit. The test circuit is provided with a feedback path so that the test circuit and feedback path together form a free-running oscillator. The oscillator then automatically provides its own test signal that includes alternating rising and falling signal transitions on the test-circuit input node. These signal transitions are counted over a predetermined time period to establish the period of the oscillator. The period of the oscillator is then related to the average signal propagation delay through the test circuit. The invention can be applied to synchronous components that might fail to oscillate by connecting the asynchronous set or clear terminal to the output terminal so that the oscillator oscillates at a frequency determined by the clock-to-out delay of those components. The configuration can thus be used to characterize synchronous and asynchronous components to provide data for predicting the timing behavior of circuits that include those or similar components.
摘要翻译：电路通过选定的测试电路测量信号传播延迟。测试电路设置有反馈路径，使得测试电路和反馈路径一起形成自由振荡的振荡器。然后振荡器自动提供自己的测试信号，包括在测试电路输入节点上交替的上升和下降信号转换。这些信号转换在预定的时间周期内进行计数，以建立振荡器的周期。然后振荡器的周期与通过测试电路的平均信号传播延迟相关。本发明可以应用于通过将异步设置或清除端子连接到输出端子而可能无法振荡的同步部件，使得振荡器以由那些部件的时钟到输出延迟确定的频率振荡。因此，该配置可以用于表征同步和异步组件，以提供用于预测包括那些或类似组件的电路的定时行为的数据。

7. 发明授权

US08129834B2 Integral metal structure with conductive post portions 有权
标题翻译：具有导电柱部分的整体金属结构
公开(公告)号：US08129834B2
公开(公告)日：2012-03-06
申请号：US12321833
申请日：2009-01-26
申请人： Robert O. Conn
发明人： Robert O. Conn
IPC分类号： H01L23/482 , H01L23/49 , H01L23/492 , H01L23/367
CPC分类号： H01L23/50 , H01L2924/0002 , H01L2924/00
摘要： A plurality of FPGA dice is disposed upon a semiconductor substrate. In order to supply the immense power required by the plurality of FPGA dice, power is routed through the semiconductor substrate vertically from thick metal layers and large integral metal structures located on the other side of the semiconductor substrate. Because the semiconductor substrate has a different coefficient of thermal linear expansion than metal layers in contact with the substrate, delamination may occur when the structure is subject to changes in temperature. To prevent delamination of metal layers connected to the semiconductor substrate and in electrical contact with the integral metal structures, the integral metal structures are manufactured with an array of post portions. During changes in temperature, the post portions of the integral metal structures bend and slide relative to metal layers connected to the semiconductor substrate and prevent linear stresses that may otherwise cause delamination.
摘要翻译：多个FPGA管芯设置在半导体衬底上。为了提供多个FPGA芯片所需的巨大功率，功率从位于半导体衬底另一侧的厚金属层和大的整体金属结构垂直地穿过半导体衬底。由于半导体衬底与与衬底接触的金属层具有不同的热线性膨胀系数，所以当结构经受温度变化时，可能发生分层。为了防止与半导体衬底连接并与整体金属结构电接触的金属层的分层，整体金属结构被制成具有一定数量的柱部分。在温度变化期间，整体金属结构的后部相对于连接到半导体衬底的金属层弯曲和滑动，并且防止否则会引起分层的线性应力。

8. 发明申请

US20110239456A1 In system reflow of low temperature eutectic bond balls 失效
标题翻译：在低温共晶粘结球的系统回流中
公开(公告)号：US20110239456A1
公开(公告)日：2011-10-06
申请号：US12798132
申请日：2010-03-30
申请人： Robert O. Conn , Daniel S. Stevenson
发明人： Robert O. Conn , Daniel S. Stevenson
IPC分类号： H05K3/34
CPC分类号： H01L24/81 , H01L23/147 , H01L23/49816 , H01L23/49827 , H01L23/50 , H01L23/5384 , H01L24/13 , H01L24/16 , H01L24/97 , H01L25/0655 , H01L2224/05147 , H01L2224/10135 , H01L2224/10165 , H01L2224/13109 , H01L2224/13111 , H01L2224/13113 , H01L2224/13562 , H01L2224/13655 , H01L2224/16225 , H01L2224/16227 , H01L2224/16237 , H01L2224/8114 , H01L2224/81141 , H01L2224/81191 , H01L2224/81234 , H01L2224/81815 , H01L2224/97 , H01L2924/01322 , H01L2924/12041 , H01L2924/14 , H01L2924/15311 , H05K3/3436 , H05K3/3494 , H05K2203/047 , H05K2203/163 , Y02P70/613 , Y10T29/49128 , Y10T29/4913 , Y10T29/49144 , Y10T29/49147 , Y10T29/49169 , H01L2924/00 , H01L2924/00014 , H01L2924/00012
摘要： Low temperature bond balls connect two structures having disparate coefficients of linear thermal expansion. An integrated circuit is made to heat the device such that the low temperature bond balls melt. After melting, the bond balls solidify, and the device is operated with the bond balls solidified. In one example, one of the two structures is a semiconductor substrate, and the other structure is a printed circuit board. The integrated circuit is a die mounted to the semiconductor substrate. The bond balls include at least five percent indium, and the integrated circuit is an FPGA loaded with a bit stream. The bit stream configures the FPGA such that the FPGA has increased power dissipation, which melts the balls. After the melting, a second bit stream is loaded into the FPGA and the FPGA is operated in a normal user-mode using the second bit stream.
摘要翻译：低温焊球连接两个具有不同的线性热膨胀系数的结构。制造集成电路以加热该器件，使得低温接合球熔化。熔化后，粘结球固化，并且使粘合球固化的装置进行操作。在一个示例中，两个结构之一是半导体衬底，而另一个结构是印刷电路板。集成电路是安装到半导体衬底的裸片。结合球包括至少5％的铟，并且集成电路是装载有位流的FPGA。位流配置FPGA，使得FPGA具有增加的功率耗散，其熔化了球。熔化后，将第二位流装载到FPGA中，并使用第二位流以正常用户模式操作FPGA。

9. 发明授权

US07709966B2 Large substrate structural vias 有权
标题翻译：大衬底结构通孔
公开(公告)号：US07709966B2
公开(公告)日：2010-05-04
申请号：US11952495
申请日：2007-12-07
申请人： Robert O. Conn
发明人： Robert O. Conn
IPC分类号： H01L23/48
CPC分类号： H01L23/49827 , H01L21/486 , H01L23/147 , H01L2924/0002 , H01L2924/14 , H01L2924/1433 , H01L2924/15165 , H01L2924/157 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , Y10T29/49117 , Y10T29/49165 , H01L2924/00
摘要： An electronic package and methods by which the package reduces thermal fatigue failure of conductors in the electronic package. The electronic package includes a carrier substrate having first and second surfaces and a plurality of anchor vias having a via material extending from the first surface toward the second surface. The electronic package includes a first conducting layer having a length and a width extending laterally in two dimensions across a major part of the first surface of the carrier substrate. The anchor vias have plural attachments along the length and the width of the first conducting layer to secure the first conducting layer to the carrier substrate.
摘要翻译：电子封装和封装的方法减少电子封装中导体的热疲劳失效。电子封装包括具有第一和第二表面的载体基板和具有从第一表面向第二表面延伸的通孔材料的多个锚定通孔。电子封装包括第一导电层，第一导电层的长度和宽度横向延伸穿过载体衬底的第一表面的主要部分。锚定通孔沿着第一导电层的长度和宽度具有多个附着物，以将第一导电层固定到载体基底。

10. 发明申请

US20090079058A1 Semiconductor substrate elastomeric stack 有权
标题翻译：半导体衬底弹性体叠层
公开(公告)号：US20090079058A1
公开(公告)日：2009-03-26
申请号：US11975007
申请日：2007-10-16
申请人： Robert O. Conn
发明人： Robert O. Conn
IPC分类号： H01L23/538 , H01L21/58
CPC分类号： H05K7/20927 , H01L23/473 , H01L23/481 , H01L24/05 , H01L24/29 , H01L24/32 , H01L25/0652 , H01L2224/0557 , H01L2224/29101 , H01L2225/0652 , H01L2225/06527 , H01L2225/06541 , H01L2225/06555 , H01L2225/06572 , H01L2225/06589 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01077 , H01L2924/014 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , H01L2924/00 , H01L2224/05552
摘要： A reconfigurable high performance computer occupies less than 360 cubic inches and has an approximate compute power of 0.7 teraflops per second while consuming less than 1000 watts. The computer includes a novel stack of semiconductor substrate assemblies. Some semiconductor substrate assemblies involve field programmable gate array (FPGA) dice that are directly surface mounted, as bare die, to a semiconductor substrate. Other semiconductor substrate assemblies of the stack involve bare memory integrated circuit dice that are directly surface mounted to a semiconductor substrate. Elastomeric connectors interconnect adjacent semiconductor substrates proceeding down the stack. Tines of novel comb-shaped power bus bar assembly structures extend into the stack to supply DC supply voltages. The supply voltages are supplied from bus bars, through vias in the semiconductor substrates, and to the integrated circuits on the other side of the substrates. The power bus bars also serve as capacitors and guides for liquid coolant.
摘要翻译：可重新配置的高性能计算机占用小于360立方英寸，并且具有每秒0.7 teraflops的近似计算能力，同时消耗少于1000瓦特。该计算机包括一组新的半导体衬底组件。一些半导体衬底组件涉及作为裸芯片直接表面安装到半导体衬底的现场可编程门阵列（FPGA）裸片。堆叠的其他半导体衬底组件包括直接表面安装到半导体衬底的裸存储器集成电路裸片。弹性连接器将相邻的半导体衬底互相连接，沿堆叠进入。新颖的梳状电源母线组合结构的齿条延伸到堆叠中以提供直流电源电压。电源电压由母线，半导体衬底中的通孔以及衬底另一侧的集成电路提供。电力母线还用作液体冷却剂的电容器和导轨。

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