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1. 发明授权

US08589839B2 ESD protection validator, an ESD validation system and a method of validating ESD protection for an IC 有权
标题翻译： ESD保护验证器，ESD验证系统和验证IC的ESD保护的方法
公开(公告)号：US08589839B2
公开(公告)日：2013-11-19
申请号：US12506597
申请日：2009-07-21
申请人： Gianluca Boselli , Jonathan S. Brodsky , John E. Kunz, Jr.
发明人： Gianluca Boselli , Jonathan S. Brodsky , John E. Kunz, Jr.
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , H01L27/0248
摘要： Disclosed is an electrostatic discharge (ESD) protection validator, a method of validating ESD protection for an IC and an ESD validation system. In one embodiment, the ESD protection validator includes: (1) a circuit analyzer configured to compare component information of the IC with predefined ESD protection elements to identify ESD cells of the IC and (2) an ESD cell verifier configured to compare physical attributes associated with the identified ESD cells to ESD protection requirements and determine compliance therewith.
摘要翻译：公开了一种静电放电（ESD）保护验证器，一种用于对IC和ESD验证系统进行ESD保护的验证方法。在一个实施例中，ESD保护验证器包括：（1）电路分析器，被配置为将IC的组件信息与预定义的ESD保护元件进行比较，以识别IC的ESD单元;以及（2）ESD单元验证器，被配置为将相关的物理属性将所识别的ESD电池与ESD保护要求相结合，并确定其符合性。

2. 发明授权

US08176460B2 Method of optimizing ESD protection for an IC, an ESD protection optimizer and an ESD protection optimization system 有权
标题翻译：优化IC的ESD保护方法，ESD保护优化器和ESD保护优化系统
公开(公告)号：US08176460B2
公开(公告)日：2012-05-08
申请号：US12434578
申请日：2009-05-01
申请人： Gianluca Boselli , Jonathan S. Brodsky , John E. Kunz, Jr.
发明人： Gianluca Boselli , Jonathan S. Brodsky , John E. Kunz, Jr.
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/5045 , H01L27/0248
摘要： An ESD protection optimizer, a method of optimizing ESD protection for an IC and an ESD protection optimization system is disclosed. In one embodiment, the ESD protection optimizer includes: (1) a circuit analyzer configured to identify ESD cells and circuitry of the IC by comparing component information of the IC with predefined ESD protection elements and predefined circuit topologies and (2) an ESD resistance determiner configured to calculate a resistance value to couple in series with the circuitry, the resistance value based on protection cell physical attributes associated with the identified ESD cells and circuitry physical attributes associated with the identified circuitry.
摘要翻译：公开了ESD保护优化器，一种优化IC的ESD保护和ESD保护优化系统的方法。在一个实施例中，ESD保护优化器包括：（1）电路分析器，被配置为通过将IC的组件信息与预定义的ESD保护元件和预定义的电路拓扑结构进行比较来识别IC的ESD单元和电路，以及（2）ESD电阻确定器被配置为计算与所述电路串联耦合的电阻值，所述电阻值基于与所识别的ESD单元相关联的保护单元物理属性和与所识别的电路相关联的电路物理属性。

3. 发明申请

US20100169854A1 ESD PROTECTION VALIDATOR, AN ESD VALIDATION SYSTEM AND A METHOD OF VALIDATING ESD PROTECTION FOR AN IC 有权
标题翻译： ESD保护验证器，ESD验证系统和一种用于对IC进行ESD保护的方法
公开(公告)号：US20100169854A1
公开(公告)日：2010-07-01
申请号：US12506597
申请日：2009-07-21
申请人： Gianluca Boselli , Jonathan S. Brodsky , John E. Kunz, JR.
发明人： Gianluca Boselli , Jonathan S. Brodsky , John E. Kunz, JR.
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , H01L27/0248
摘要： Disclosed is an electrostatic discharge (ESD) protection validator, a method of validating ESD protection for an IC and an ESD validation system. In one embodiment, the ESD protection validator includes: (1) a circuit analyzer configured to compare component information of the IC with predefined ESD protection elements to identify ESD cells of the IC and (2) an ESD cell verifier configured to compare physical attributes associated with the identified ESD cells to ESD protection requirements and determine compliance therewith.
摘要翻译：公开了一种静电放电（ESD）保护验证器，一种用于对IC和ESD验证系统进行ESD保护的验证方法。在一个实施例中，ESD保护验证器包括：（1）电路分析器，被配置为将IC的组件信息与预定义的ESD保护元件进行比较，以识别IC的ESD单元;以及（2）ESD单元验证器，被配置为将相关的物理属性将所识别的ESD电池与ESD保护要求相结合，并确定其符合性。

4. 发明申请

US20100169064A1 SYSTEM, AN APPARATUS AND A METHOD FOR PERFORMING CHIP-LEVEL ELECTROSTATIC DISCHARGE SIMULATIONS 有权
标题翻译：系统，装置和执行芯片级静电放电模拟的方法
公开(公告)号：US20100169064A1
公开(公告)日：2010-07-01
申请号：US12434573
申请日：2009-05-01
申请人： Gianluca Boselli , Jonathan S. Brodsky , John E. Kunz, JR.
发明人： Gianluca Boselli , Jonathan S. Brodsky , John E. Kunz, JR.
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A modeler for components of an IC under ESD conditions, a method of simulating ESD behavior of an IC and an ESD simulation system. In one embodiment, the modeler includes: (1) a circuit analyzer configured to provide identified ESD cells and circuitry of the IC by comparing component information of the IC with predefined ESD protection elements and predefined circuit topologies and (2) a model generator configured to create linearized models of the identified ESD cells and the identified circuitry based on physical attributes associated with the identified ESD cells and the identified circuitry, wherein a combination of the linearized models represent operation of the IC component under ESD conditions.
摘要翻译：用于ESD条件下的IC器件的建模器，一种模拟IC ESD ESD模拟系统的ESD方法。在一个实施例中，建模器包括：（1）电路分析器，被配置为通过将IC的组件信息与预定义的ESD保护元件和预定义的电路拓扑结构相比较来提供所识别的ESD单元和IC的电路，以及（2）模型发生器，基于与所识别的ESD单元和所识别的电路相关联的物理属性，创建所识别的ESD单元和所识别的电路的线性化模型，其中线性化模型的组合表示在ESD条件下IC组件的操作。

5. 发明授权

US08306804B2 System, an apparatus and a method for performing chip-level electrostatic discharge simulations 有权
标题翻译：用于执行芯片级静电放电模拟的系统，装置和方法
公开(公告)号：US08306804B2
公开(公告)日：2012-11-06
申请号：US12434573
申请日：2009-05-01
申请人： Gianluca Boselli , Jonathan S. Brodsky , John E. Kunz, Jr.
发明人： Gianluca Boselli , Jonathan S. Brodsky , John E. Kunz, Jr.
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A modeler for components of an IC under ESD conditions, a method of simulating ESD behavior of an IC and an ESD simulation system. In one embodiment, the modeler includes: (1) a circuit analyzer configured to provide identified ESD cells and circuitry of the IC by comparing component information of the IC with predefined ESD protection elements and predefined circuit topologies and (2) a model generator configured to create linearized models of the identified ESD cells and the identified circuitry based on physical attributes associated with the identified ESD cells and the identified circuitry, wherein a combination of the linearized models represent operation of the IC component under ESD conditions.
摘要翻译：用于ESD条件下的IC器件的建模器，一种模拟IC ESD ESD模拟系统的ESD方法。在一个实施例中，建模器包括：（1）电路分析器，被配置为通过将IC的组件信息与预定义的ESD保护元件和预定义的电路拓扑结构相比较来提供所识别的ESD单元和IC的电路，以及（2）模型发生器，基于与所识别的ESD单元和所识别的电路相关联的物理属性，创建所识别的ESD单元和所识别的电路的线性化模型，其中线性化模型的组合表示在ESD条件下IC组件的操作。

6. 发明申请

US20100169845A1 METHOD OF OPTIMIZING ESD PROTECTION FOR AN IC, AN ESD PROTECTION OPTIMIZER AND AN ESD PROTECTION OPTIMIZATION SYSTEM 有权
标题翻译：优化IC，ESD保护优化器和ESD保护优化系统的ESD保护方法
公开(公告)号：US20100169845A1
公开(公告)日：2010-07-01
申请号：US12434578
申请日：2009-05-01
申请人： Gianluca Boselli , Jonathan S. Brodsky , John E. Kunz, JR.
发明人： Gianluca Boselli , Jonathan S. Brodsky , John E. Kunz, JR.
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , H01L27/0248
摘要： An ESD protection optimizer, a method of optimizing ESD protection for an IC and an ESD protection optimization system is disclosed. In one embodiment, the ESD protection optimizer includes: (1) a circuit analyzer configured to identify ESD cells and circuitry of the IC by comparing component information of the IC with predefined ESD protection elements and predefined circuit topologies and (2) an ESD resistance determiner configured to calculate a resistance value to couple in series with the circuitry, the resistance value based on protection cell physical attributes associated with the identified ESD cells and circuitry physical attributes associated with the identified circuitry.
摘要翻译：公开了ESD保护优化器，一种优化IC的ESD保护和ESD保护优化系统的方法。在一个实施例中，ESD保护优化器包括：（1）电路分析器，被配置为通过将IC的组件信息与预定义的ESD保护元件和预定义的电路拓扑结构进行比较来识别IC的ESD单元和电路，以及（2）ESD电阻确定器被配置为计算与所述电路串联耦合的电阻值，所述电阻值基于与所识别的ESD单元相关联的保护单元物理属性和与所识别的电路相关联的电路物理属性。

7. 发明授权

US07414287B2 System and method for making a LDMOS device with electrostatic discharge protection 有权
标题翻译：制造具有静电放电保护功能的LDMOS器件的系统和方法
公开(公告)号：US07414287B2
公开(公告)日：2008-08-19
申请号：US11063312
申请日：2005-02-21
申请人： Sameer P. Pendharkar , Jonathan S. Brodsky
发明人： Sameer P. Pendharkar , Jonathan S. Brodsky
IPC分类号： H01L29/94
CPC分类号： H01L29/66681 , H01L27/088 , H01L29/086 , H01L29/42368 , H01L29/7436 , H01L29/749 , H01L29/7816
摘要： A semiconductor device includes one or more LDMOS transistors and one of more SCR-LDMOS transistors. Each LDMOS transistor includes a LDMOS well of a first conductivity type, a LDMOS source region of a second conductivity type formed in the LDMOS well, and a LDMOS drain region of a second conductivity type separated from the LDMOS well by a LDMOS drift region of the second conductivity type. Each SCR-LDMOS transistor comprising a SCR-LDMOS well of the first conductivity type, a SCR-LDMOS source region of the second conductivity type formed in the SCR-LDMOS well, a SCR-LDMOS drain region of a second conductivity type, and a anode region of the first conductivity type between the SCR-LDMOS drain region and the SCR-LDMOS drift region. The anode region is separated from the SCR-LDMOS well by a SCR-LDMOS drift region of the second conductivity type.
摘要翻译：半导体器件包括一个或多个LDMOS晶体管和一个更多的SCR-LDMOS晶体管。每个LDMOS晶体管包括第一导电类型的LDMOS阱，在LDMOS阱中形成的第二导电类型的LDMOS源极区，以及由LDMOS阱的LDMOS漂移区分离的第二导电类型的LDMOS漏极区，第二导电类型。每个SCR-LDMOS晶体管包括第一导电类型的SCR-LDMOS阱，形成在SCR-LDMOS阱中的第二导电类型的SCR-LDMOS源区，第二导电类型的SCR-LDMOS漏极区和 SCR-LDMOS漏区和SCR-LDMOS漂移区之间的第一导电类型的阳极区。阳极区域通过第二导电类型的SCR-LDMOS漂移区与SCR-LDMOS阱分离。

8. 发明授权

US07687853B2 System and method for making a LDMOS device with electrostatic discharge protection 有权
标题翻译：制造具有静电放电保护功能的LDMOS器件的系统和方法
公开(公告)号：US07687853B2
公开(公告)日：2010-03-30
申请号：US12173418
申请日：2008-07-15
申请人： Sameer P Pendharkar , Jonathan S. Brodsky
发明人： Sameer P Pendharkar , Jonathan S. Brodsky
IPC分类号： H01L29/94
CPC分类号： H01L29/66681 , H01L27/088 , H01L29/086 , H01L29/42368 , H01L29/7436 , H01L29/749 , H01L29/7816
摘要： A semiconductor device includes one or more LDMOS transistors and one of more SCR-LDMOS transistors. Each LDMOS transistor includes a LDMOS well of a first conductivity type, a LDMOS source region of a second conductivity type formed in the LDMOS well, and a LDMOS drain region of a second conductivity type separated from the LDMOS well by a LDMOS drift region of the second conductivity type. Each SCR-LDMOS transistor comprising a SCR-LDMOS well of the first conductivity type, a SCR-LDMOS source region of the second conductivity type formed in the SCR-LDMOS well, a SCR-LDMOS drain region of a second conductivity type, and a anode region of the first conductivity type between the SCR-LDMOS drain region and the SCR-LDMOS drift region. The anode region is separated from the SCR-LDMOS well by a SCR-LDMOS drift region of the second conductivity type.
摘要翻译：半导体器件包括一个或多个LDMOS晶体管和一个更多的SCR-LDMOS晶体管。每个LDMOS晶体管包括第一导电类型的LDMOS阱，在LDMOS阱中形成的第二导电类型的LDMOS源极区，以及由LDMOS阱的LDMOS漂移区分离的第二导电类型的LDMOS漏极区，第二导电类型。每个SCR-LDMOS晶体管包括第一导电类型的SCR-LDMOS阱，形成在SCR-LDMOS阱中的第二导电类型的SCR-LDMOS源区，第二导电类型的SCR-LDMOS漏极区和 SCR-LDMOS漏区和SCR-LDMOS漂移区之间的第一导电类型的阳极区。阳极区域通过第二导电类型的SCR-LDMOS漂移区与SCR-LDMOS阱分离。

9. 发明授权

US08384127B1 Bi-directional ESD protection circuit 有权
公开(公告)号：US08384127B1
公开(公告)日：2013-02-26
申请号：US09498677
申请日：2000-02-07
申请人： Robert Steinhoff , Jonathan S. Brodsky , Thomas A. Vrotsos
发明人： Robert Steinhoff , Jonathan S. Brodsky , Thomas A. Vrotsos
IPC分类号： H01L29/747
CPC分类号： H01L27/0277 , H01L27/0274 , H01L29/0692 , H01L29/1083 , H01L29/41758 , H01L29/4238 , H01L29/78
摘要： A structure is designed with an external terminal (100) and a reference terminal (102). A first transistor (106) is formed on a substrate. The first transistor has a current path coupled between the external terminal and the reference terminal. A second transistor (118) has a current path coupled between the external terminal and the substrate. A third transistor (120) has a current path coupled between the substrate and the reference terminal.

10. 发明申请

US20080296669A1 SYSTEM AND METHOD FOR MAKING A LDMOS DEVICE WITH ELECTROSTATIC DISCHARGE PROTECTION 有权
标题翻译：用于制造具有静电放电保护的LDMOS器件的系统和方法
公开(公告)号：US20080296669A1
公开(公告)日：2008-12-04
申请号：US12173418
申请日：2008-07-15
申请人： Sameer P. Pendharkar , Jonathan S. Brodsky
发明人： Sameer P. Pendharkar , Jonathan S. Brodsky
IPC分类号： H01L29/78
CPC分类号： H01L29/66681 , H01L27/088 , H01L29/086 , H01L29/42368 , H01L29/7436 , H01L29/749 , H01L29/7816
摘要： A semiconductor device includes one or more LDMOS transistors and one of more SCR-LDMOS transistors. Each LDMOS transistor includes a LDMOS well of a first conductivity type, a LDMOS source region of a second conductivity type formed in the LDMOS well, and a LDMOS drain region of a second conductivity type separated from the LDMOS well by a LDMOS drift region of the second conductivity type. Each SCR-LDMOS transistor comprising a SCR-LDMOS well of the first conductivity type, a SCR-LDMOS source region of the second conductivity type formed in the SCR-LDMOS well, a SCR-LDMOS drain region of a second conductivity type, and a anode region of the first conductivity type between the SCR-LDMOS drain region and the SCR-LDMOS drift region. The anode region is separated from the SCR-LDMOS well by a SCR-LDMOS drift region of the second conductivity type.
摘要翻译：半导体器件包括一个或多个LDMOS晶体管和一个更多的SCR-LDMOS晶体管。每个LDMOS晶体管包括第一导电类型的LDMOS阱，在LDMOS阱中形成的第二导电类型的LDMOS源极区，以及由LDMOS阱的LDMOS漂移区分离的第二导电类型的LDMOS漏极区，第二导电类型。每个SCR-LDMOS晶体管包括第一导电类型的SCR-LDMOS阱，形成在SCR-LDMOS阱中的第二导电类型的SCR-LDMOS源区，第二导电类型的SCR-LDMOS漏极区和 SCR-LDMOS漏区和SCR-LDMOS漂移区之间的第一导电类型的阳极区。阳极区域通过第二导电类型的SCR-LDMOS漂移区与SCR-LDMOS阱分离。

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