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1. 发明授权

US5341322A Bit level pipeline divide circuit and method therefor 失效
标题翻译：位级流水线分割电路及其方法
公开(公告)号：US5341322A
公开(公告)日：1994-08-23
申请号：US881336
申请日：1992-05-11
申请人： Gerhard P. Fettweis , Herbert R. Dawid
发明人： Gerhard P. Fettweis , Herbert R. Dawid
IPC分类号： G06F7/52 , G06F7/544
CPC分类号： G06F7/5312 , G06F7/535 , G06F7/5443 , G06F2207/3836 , G06F2207/3884
摘要： A divide circuit having bit level pipeline capability uses an array of bit level carry save adders with each carry save adder having a corresponding absolute value bit level circuit. In one or two's complement notation, the carry save adders subtract the binary values supplied thereto and generates an intermediate binary signal which is supplied to the absolute value circuit. The absolute value circuit determines the absolute value of the binary number supplied thereto. The circuit performs division in accordance with the following algorithm:Q.sub.w 1I=W-1 to 0N=N-DS=Signbit (N)Q.sub.I =S (EXOR) Q.sub.I+1N=.vertline.N.vertline.D=D/2ENDA recursive divide circuit employing an array of carry save adders and absolute value bit level circuits achieves full pipeline bit level capability.
摘要翻译：具有位电平流水线能力的分频电路使用具有相应绝对值位电平电路的每个进位存储加法器的位电平进位存储加法器阵列。在一个或两个补码符号中，进位存储加法器减去提供给它的二进制值，并产生提供给绝对值电路的中间二进制信号。绝对值电路确定提供给它的二进制数的绝对值。电路根据以下算法进行除法：Qw1 I = W-1至0 N = N-D S =信号（N）QI = S（EXOR）QI + 1 N = | N | D = D / 2 END采用进位保存加法器和绝对值位电平电路阵列的递归分频电路实现完整的管道位电平能力。

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