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    • 7. 发明授权
    • Debug and video queue for multi-processor chip
    • 多处理器芯片的调试和视频队列
    • US5848264A
    • 1998-12-08
    • US740248
    • 1996-10-25
    • Brian R. BairdDavid E. RichterShalesh ThusooDavid M. StarkJames S. Blomgren
    • Brian R. BairdDavid E. RichterShalesh ThusooDavid M. StarkJames S. Blomgren
    • G06F11/36G06F9/455
    • G06F11/3636G06F11/3656
    • A microprocessor die contains several processor cores and a shared cache. Trigger conditions for one or more of the processor cores are programmed into debug registers. When a trigger is detected, a trace record is generated and loaded into a debug queue on the microprocessor die. Several trace records from different processor cores can be rapidly generated and loaded into the debug queue. The external interface cannot transfer these trace records to an external in-circuit emulator (ICE) at the rate generated. The debug queue transfers trace records to the external ICE using a dedicated bus to the ICE so that bandwidth is not taken from the memory bus. The memory bus is not slowed for debugging, providing a more realistic debugging session. The debug buffer is also used as a video FIFO for buffering pixels for display on a monitor. The dedicated bus is connected to an external DAC rather than to the external ICE when debugging is not being performed.
    • 微处理器芯片包含几个处理器内核和一个共享缓存。 一个或多个处理器内核的触发条件被编程到调试寄存器中。 当检测到触发时,生成跟踪记录并加载到微处理器管芯上的调试队列中。 可以快速生成来自不同处理器内核的多个跟踪记录,并将其加载到调试队列中。 外部接口不能以生成的速率将这些跟踪记录传输到外部在线仿真器(ICE)。 调试队列使用专用总线将ICE跟踪记录传输到外部ICE,从而不会从存储器总线获取带宽。 内存总线调试速度并不慢,提供了更实际的调试会话。 调试缓冲区还用作视频FIFO,用于缓冲显示器上的像素。 当不进行调试时,专用总线连接到外部DAC而不是外部ICE。