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1. 发明授权

US5055897A Semiconductor cell for neural network and the like 失效
标题翻译：神经网络的半导体细胞和类似的
公开(公告)号：US5055897A
公开(公告)日：1991-10-08
申请号：US225035
申请日：1988-07-27
申请人： George R. Canepa , Mark A. Holler , Simon M. Tam
发明人： George R. Canepa , Mark A. Holler , Simon M. Tam
IPC分类号： G06G7/60 , G06F15/18 , G06N3/06 , G06N3/063 , G06N99/00 , H01L21/82 , H01L21/8238 , H01L21/8247 , H01L27/00 , H01L27/092 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/115 , G06N3/0635
摘要： A cell employing floating gate storage device particularly suited for neural networks. The floating gate from the floating gate device extends to and becomes part of a second, field effect device. Current through the second device is affected by the charge on the floating gate. The weighting factor for the cell is determined by the amount of charge on the floating gate. By charging the floating gate to various levels, a continuum of weighting factors is obtained. Multiplication is obtained since the current through the second device is a function of the weighting factor.
摘要翻译：采用特别适用于神经网络的浮动门存储装置的小区。来自浮动栅极器件的浮动栅极延伸到并成为第二场效应器件的一部分。通过第二器件的电流受浮栅上的电荷的影响。电池的加权系数由浮动栅极上的电荷量决定。通过将浮动门充电到各种水平，获得连续的加权因子。获得乘法是因为通过第二装置的电流是加权因子的函数。

2. 发明授权

US5146602A Method of increasing the accuracy of an analog neural network and the like 失效
标题翻译：提高模拟神经网络精度的方法等
公开(公告)号：US5146602A
公开(公告)日：1992-09-08
申请号：US634033
申请日：1990-12-26
申请人： Mark A. Holler , Simon M. Tam
发明人： Mark A. Holler , Simon M. Tam
IPC分类号： G06F15/18 , G06G7/60 , G06N3/063 , G06N99/00 , G11C27/00 , H01L29/788
CPC分类号： H01L29/7887 , G06N3/0635 , G11C27/005
摘要： A method for increasing the accuracy of an analog neural network which computers a sum-of-products between an input vector and a stored weight pattern is described. In one embodiment of the present invention, the method comprises initially training the network by programming the synapses with a certain weight pattern. The training may be carried out using any standard learning algorithm. Preferably, a back-propagation learning algorithm is employed.Next, network is baked at an elevated temperature to effectuate a change in the weight pattern previously programmed during initial training. This change results from a charge redistribution which occurs within each of the synapses of the network. After baking, the network is then retrained to compensate for the change resulting from the charge redistribution. The baking and retraining steps may be successively repeated to increase the accuracy of the neural network to any desired level.
摘要翻译：描述了一种用于增加计算输入向量和存储的权重模式之和的乘积的模拟神经网络的精度的方法。在本发明的一个实施例中，该方法包括通过以某种权重模式编程突触来初始训练网络。可以使用任何标准学习算法进行训练。优选地，采用反向传播学习算法。接下来，在升高的温度下烘烤网络，以实现在初始训练期间先前编程的重量模式的变化。这种变化是由于网络每个突触中发生的电荷再分配产生的。烘烤后，网络再次进行补充，以补偿由电荷重新分配引起的变化。烘焙和再培训步骤可以连续重复，以将神经网络的精度提高到任何所需的水平。

3. 发明授权

US4950917A Semiconductor cell for neural network employing a four-quadrant multiplier 失效
标题翻译：使用四象限乘法器的神经网络半导体单元
公开(公告)号：US4950917A
公开(公告)日：1990-08-21
申请号：US283553
申请日：1988-12-09
申请人： Mark A. Holler , Simon M. Tam , Ronald G. Benson , Hernan A. Castro
发明人： Mark A. Holler , Simon M. Tam , Ronald G. Benson , Hernan A. Castro
IPC分类号： G06G7/60 , G06F15/18 , G06N3/06 , G06N3/063 , G06N99/00 , H01L21/82 , H01L21/8238 , H01L21/8247 , H01L27/00 , H01L27/092 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/115 , G06N3/0635
摘要： A synapse cell for use in providing a weighted connection strength is disclosed. The cell employs a four-quadrant multiplier and a pair of floating gate devices. Various charge levels are programmed onto the floating gate devices, establishing weight and reference levels. These levels affect the current flowing through the multiplier. The output of the cell thus becomes a multiple of the input and the programmed charge difference.
摘要翻译：公开了一种用于提供加权连接强度的突触细胞。该单元采用四象限乘法器和一对浮栅器件。各种电荷电平被编程到浮动栅极器件上，建立重量和参考电平。这些水平影响流经乘数的电流。因此，单元的输出变为输入和编程的电荷差的倍数。

4. 发明授权

US4780424A Process for fabricating electrically alterable floating gate memory devices 失效
标题翻译：用于制造电可变浮动栅极存储器件的工艺
公开(公告)号：US4780424A
公开(公告)日：1988-10-25
申请号：US101642
申请日：1987-09-28
申请人： Mark A. Holler , Simon M. Tam
发明人： Mark A. Holler , Simon M. Tam
IPC分类号： H01L21/8247 , H01L27/115 , H01L21/425 , H01L29/78
CPC分类号： H01L27/11521 , H01L27/115
摘要： A process for fabricating contactless electrically programmable and electrically erasable memory cells of the flash EPROM type. The contactless cells use elongated source and drain regions disposed beneath field oxide regions. The drain regions are shallow compared to the source regions. The source regions have more graded junctions. Floating gates are formed over a tunnel oxide (120 .ANG. thick) between the source and drain regions with word lines being disposed perpendicular to the source and drain regions. One dimension of the floating gates is formed after the word lines have been patterned by etching the first layer of polysilicon in alignment with the word lines.
摘要翻译：用于制造闪存EPROM类型的非接触式电可编程和电可擦除存储器单元的方法。非接触式电池使用设置在场氧化物区域之下的细长的源极和漏极区域。漏极区域与源极区域相比较浅。源区具有更多的分级结。浮动栅极形成在源极和漏极区域之间的隧道氧化物（120安格姆厚）上，其字线垂直于源极和漏极区域设置。在通过蚀刻与字线对准的第一层多晶硅之后，在字线被图案化之后形成浮置栅极的一个维度。

5. 发明授权

US4961002A Synapse cell employing dual gate transistor structure 失效
标题翻译：突触细胞采用双栅晶体管结构
公开(公告)号：US4961002A
公开(公告)日：1990-10-02
申请号：US419685
申请日：1989-10-11
申请人： Simon M. Tam , Mark A. Holler , Hernan A. Castro
发明人： Simon M. Tam , Mark A. Holler , Hernan A. Castro
IPC分类号： G06N3/063 , G11C15/04
CPC分类号： G06N3/0635 , G06N3/063 , G11C15/046
摘要： A synapse cell for providing a weighted connection between an input voltage line and an output summing line having an associated capacitance. Connection between input and output lines in the associative network is made using a dual-gate transistor. The transistor has a floating gate member for storing electrical charge, a pair of control gates coupled to a pair of input lines, and a drain coupled to an output summing line. The floating gate of the transistor is used for storing a charge which corresponds to the strength or weight of the neural connection. When a binary voltage pulse having a certain duration is applied to either one or both of the control gates of the transistor, a current is generated. This current acts to discharge the capacitance associated with the output summing line. Furthermore, by employing a dual-gate structure, programming disturbance of neighboring devices in the network is practically eliminated.
摘要翻译：一种用于在输入电压线和具有相关电容的输出求和线之间提供加权连接的突触单元。关联网络中的输入和输出线之间的连接是使用双栅极晶体管进行的。晶体管具有用于存储电荷的浮动栅极部件，耦合到一对输入线路的一对控制栅极和耦合到输出求和线路的漏极。晶体管的浮置栅极用于存储对应于神经连接的强度或重量的电荷。当具有一定持续时间的二进制电压脉冲被施加到晶体管的一个或两个控制栅极时，产生电流。该电流用于放电与输出求和线相关联的电容。此外，通过采用双栅结构，实际上消除了网络中相邻设备的编程干扰。

6. 发明授权

US5264734A Difference calculating neural network utilizing switched capacitors 失效
标题翻译：差分计算神经网络利用开关电容器
公开(公告)号：US5264734A
公开(公告)日：1993-11-23
申请号：US885529
申请日：1992-05-19
申请人： Mark A. Holler , Simon M. Tam , Alan H. Kramer
发明人： Mark A. Holler , Simon M. Tam , Alan H. Kramer
IPC分类号： G06F15/18 , G06G7/60 , G06N3/063 , G06N99/00 , H03K19/173 , H03K19/177 , H03K19/08
CPC分类号： G06N3/063 , G06N3/0635
摘要： A difference calculating neural network is disclosed having an array of synapse cells arranged in rows and columns along pairs of row and column lines. The cells include a pair of floating gate devices which have their control gates coupled to receive one of a pair of complementary input voltages. The floating gate devices also have complementary threshold voltages such that packets of charge are produced from the synapse cells that are proportional to the difference between the input and voltage threshold. The charge packets are accumulated by the pairs of column lines in the array.
摘要翻译：公开了一种差分计算神经网络，其具有沿着行和列线对的行和列排列的突触细胞阵列。这些单元包括一对浮置栅极器件，它们的控制栅极耦合以接收一对互补输入电压中的一个。浮置栅极器件还具有互补的阈值电压，使得从与输入和电压阈值之间的差成比例的突触电池产生电荷分组。电荷分组由阵列中的列线对累积。

7. 发明授权

US5256911A Neural network with multiplexed snyaptic processing 失效
标题翻译：神经网络复用s tic加工
公开(公告)号：US5256911A
公开(公告)日：1993-10-26
申请号：US896204
申请日：1992-06-10
申请人： Mark A. Holler , Simon M. Tam
发明人： Mark A. Holler , Simon M. Tam
IPC分类号： G06N3/063 , G06F15/18
CPC分类号： G06N3/063 , G06N3/0635
摘要： In an apparatus for multiplexed operation of multi-cell neural network, the reference vector component values are stored as differential values in pairs of floating gate transistors. A long-tail pair differential transconductance multiplier is synthesized by selectively using the floating gate transistor pairs as the current source. Appropriate transistor pairs are multiplexed into the network for forming a differential output current representative of the product of the input vector component applied to the differential input and the stored reference vector component stored in the multiplexed transistor pair that is switched into the multiplier network to function as the differential current source. Pipelining and output multiplexing is also described in other preferred embodiments for increasing the effective output bandwidth of the network.
摘要翻译：在多单元神经网络的多路复用操作装置中，参考矢量分量值作为浮动栅极晶体管对中的差分值存储。通过选择性地使用浮栅晶体管对作为电流源来合成长尾对差分跨导乘法器。合适的晶体管对被多路复用到网络中，用于形成代表施加到差分输入的输入矢量分量与存储在多路复用晶体管对中的存储的参考矢量分量的乘积的差分输出电流，所述基准矢量分量被切换到乘法器网络中，以用作差动电流源。在其他优选实施例中还描述了流水线和输出多路复用以增加网络的有效输出带宽。

8. 发明授权

US5268320A Method of increasing the accuracy of an analog circuit employing floating gate memory devices 失效
标题翻译：使用浮动栅极存储器件的模拟电路的精度提高的方法
公开(公告)号：US5268320A
公开(公告)日：1993-12-07
申请号：US865451
申请日：1992-04-09
申请人： Mark A. Holler , Simon M. Tam
发明人： Mark A. Holler , Simon M. Tam
IPC分类号： G06N3/063 , G11C27/00 , H01L29/788 , H01L21/265 , H01L21/76
CPC分类号： G06N3/0635 , G11C27/005 , H01L29/7887 , Y10S438/91
摘要： A method for increasing the accuracy of an analog neural network which computers a sum-of-products between an input vector and a stored weight pattern is described. In one embodiment of the present invention, the method comprises initially training the network by programming the synapses with a certain weight pattern. The training may be carried out using any standard learning algorithm. Preferably, a back-propagation learning algorithm is employed.Next, the network is baked at an elevated temperature to effectuate a change in the weight pattern previously programmed during initial training. This change results from a charge redistribution which occurs within each of the synapses of the network. After baking, the network is then retrained to compensate for the change resulting from the charge redistribution. The baking and retraining steps may be successively repeated to increase the accuracy of the neural network to any desired level.
摘要翻译：描述了一种用于增加计算输入向量和存储的权重模式之和的乘积的模拟神经网络的精度的方法。在本发明的一个实施例中，该方法包括通过以某种权重模式编程突触来初始训练网络。可以使用任何标准学习算法进行训练。优选地，采用反向传播学习算法。接下来，网络在升高的温度下烘烤以实现初始训练中先前编程的重量模式的变化。这种变化是由于网络每个突触中发生的电荷再分配产生的。烘烤后，网络再次进行补充，以补偿由电荷重新分配引起的变化。烘焙和再培训步骤可以连续重复，以将神经网络的精度提高到任何所需的水平。

9. 发明授权

US5087826A Multi-layer neural network employing multiplexed output neurons 失效
标题翻译：多层神经网络采用复用输出神经元
公开(公告)号：US5087826A
公开(公告)日：1992-02-11
申请号：US635231
申请日：1990-12-28
申请人： Mark A. Holler , Simon M. Tam
发明人： Mark A. Holler , Simon M. Tam
IPC分类号： G06F15/18 , G06G7/60 , G06N3/04 , G06N99/00
CPC分类号： G06N3/0445
摘要： A multi-layer electrically trainable analog neural network employing multiplexed output neurons having inputs organized into two groups, external and recurrent (i.e., feedback). Each layer of the network comprises a matrix of synapse cells which implement a matrix multiplication between an input vector and a weight matrix. In normal operation, an external input vector coupled to the first synaptic array generates a Sigmoid response at the output of a set of neurons. This output is then fed back to the next and subsequent layers of the network as a recurrent input vector. The output of second layer processing is generated by the same neurons used in first layer processing. Thus, the neural network of the present invention can handle N-layer operation by using recurrent connections and a single set of multiplexed output neurons.
摘要翻译：一种多层电可训练的模拟神经网络，其使用具有组合成两组的输入的多路复用输出神经元，外部和复发（即，反馈）。网络的每个层包括突变单元的矩阵，其实现输入向量和权重矩阵之间的矩阵乘法。在正常操作中，耦合到第一突触阵列的外部输入向量在一组神经元的输出处产生S形反应。然后将该输出作为反复输入向量反馈到网络的下一层和后续层。第二层处理的输出由第一层处理中使用的相同神经元产生。因此，本发明的神经网络可以通过使用循环连接和单组多路复用输出神经元来处理N层操作。

10. 发明授权

US5075869A Neural network exhibiting improved tolerance to temperature and power supply variations 失效
标题翻译：显示改善的耐温度和电源变化的神经网络
公开(公告)号：US5075869A
公开(公告)日：1991-12-24
申请号：US557555
申请日：1990-06-24
申请人： Mark A. Holler , Hernan A. Castro , Simon M. Tam
发明人： Mark A. Holler , Hernan A. Castro , Simon M. Tam
IPC分类号： G06N3/063
CPC分类号： G06N3/0635
摘要： An analog neural network is described which provides a means for reducing the sensitivity of the network to temperature and power supply variations. A first circuit is utilized for generating a signal which exhibits a dependence on temperature corresponding to the variation normally experienced by the network in response to a change in temperature. A second circuit is employed to generate another signal which exhibits a similar dependence, except on power supply variations. By coupling these signals as inputs to the neural network the sensitivity of the network to temperature and power supply fluctuations is essentially nulified.
摘要翻译：描述了一种模拟神经网络，其提供了降低网络对温度和电源变化的灵敏度的手段。第一电路用于产生对应于温度变化通常由网络经历的变化的温度的依赖性的信号。除了电源变化之外，使用第二电路产生表现出相似依赖性的另一信号。通过将这些信号作为输入耦合到神经网络，网络对温度和电源波动的敏感度基本上是nulified。

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