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    • 5. 发明申请
    • Assay system and methods for detecting SARS-CV
    • 检测SARS-CV检测系统和方法
    • US20050003340A1
    • 2005-01-06
    • US10609604
    • 2003-07-01
    • George Chou
    • George Chou
    • C12Q1/70C12P19/34C12Q1/68
    • C12Q1/701
    • The present invention relates to an assay system and methods for detecting SARS coronavirus (SARS-CV) from the samples (especially for urine) of suspected patient in the control of SARS to provide updated information of prognosis as well as the criteria for discharging a recovered patient from a hospital. The present invention also relates to an apparatus for performing the integration of thermal and magnetic control in the same apparatus to largely reduce the time of hybridization less than 20 minutes and the whole process of SARS-CV detection is less than 5 hours.
    • 本发明涉及一种用于检测SARS冠状病毒(SARS-CV)的方法,该SARS冠状病毒(SARS-CV)从疑似患者的样本(特别是尿液)中控制SARS,以提供更新的预后信息以及放电回收标准 病人来自医院。 本发明还涉及一种用于在相同装置中进行热和磁控制的集成的装置,以大大减少不到20分钟的杂交时间,并且SARS-CV检测的全过程小于5小时。
    • 6. 发明授权
    • Manufacture of MOSFET having LDD source/drain region
    • 具有LDD源极/漏极区域的MOSFET的制造
    • US6004852A
    • 1999-12-21
    • US864217
    • 1997-05-28
    • Wen-Kuan YehComing ChenGeorge Chou
    • Wen-Kuan YehComing ChenGeorge Chou
    • H01L21/266H01L21/336H01L21/3205
    • H01L29/66598H01L21/266H01L29/6659
    • An LDD source/drain region is manufactured adjacent a gate electrode using a single ion implantation step. The method begins by providing a polysilicon gate electrode on a gate oxide over a substrate and then providing a thin, layer of CVD oxide over the gate electrode and over the substrate. A thicker, second layer of a material different from the first silicon oxide layer is deposited over the device and is etched back to form sidewall spacer structures alongside and spaced slightly from the gate electrode. The spacer structures formed from the second layer are then used as a mask to etch the oxide layer where it is exposed over the active regions of the substrate and then the spacer structures are removed. The portion of the oxide layer that remains over the top and sides of the gate electrode and over portions of the substrate adjacent the gate electrode is then used as a mask for an ion implantation process. Implantation through the mask forms a more lightly doped and more shallowly doped region in the substrate beneath the mask and a more heavily doped and more deeply doped region in the portions of the source/drain regions that were not covered by the mask. Accordingly, implantation through the mask formed in this way forms a complete source/drain region having a lightly doped drain structure alongside the FET of the integrated circuit device. Formation of LDD source/drain regions in this manner saves a number of manufacturing steps, resulting in reduced turn around time and reduced costs.
    • 使用单个离子注入步骤在栅极附近制造LDD源极/漏极区域。 该方法开始于在衬底上的栅极氧化物上提供多晶硅栅极电极,然后在栅电极和衬底上方提供薄的CVD氧化物层。 将不同于第一氧化硅层的材料的较厚的第二层沉积在器件上并被回蚀刻以形成旁边并与栅电极稍微间隔开的侧壁间隔结构。 然后将由第二层形成的间隔结构用作掩模以蚀刻其上暴露于衬底的有源区域上的氧化物层,然后去除衬垫结构。 然后,使用保留在栅电极的顶部和侧面以及邻近栅电极的衬底的部分上的氧化物层的部分作为用于离子注入工艺的掩模。 通过掩模的植入在掩模下面的衬底中形成更轻掺杂的并且更浅掺杂的区域,并且在源极/漏极区域的未被掩模覆盖的部分中的更重掺杂和更深的掺杂区域。 因此,通过以这种方式形成的掩模的注入在集成电路器件的FET旁边形成具有轻掺杂漏极结构的完整源/漏区。 以这种方式形成LDD源极/漏极区域节省了许多制造步骤,从而减少了周转时间并降低了成本。