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1. 发明授权

US07376802B2 Memory arrangement 失效
标题翻译：内存安排
公开(公告)号：US07376802B2
公开(公告)日：2008-05-20
申请号：US10850382
申请日：2004-05-21
申请人： Georg Braun , Hermann Ruckerbauer , Maksim Kuzmenka , Siva Raghuram
发明人： Georg Braun , Hermann Ruckerbauer , Maksim Kuzmenka , Siva Raghuram
IPC分类号： G06F12/00 , G06F13/00
CPC分类号： G11C7/10 , G06F13/1678
摘要： The present invention relates to a memory arrangement having a controller and having at least one memory device. Data signals, control signals and address signals can be transferred between the controller and the memory device. The memory arrangement is designed in such a way that the data signals can be transferred via data signal lines between the controller and the memory device. The memory arrangement is furthermore designed in such a way that the control signals and the address signals can likewise be transferred via the data signal lines between the controller and the memory device.
摘要翻译：本发明涉及一种具有控制器并具有至少一个存储器件的存储器装置。数据信号，控制信号和地址信号可以在控制器和存储器件之间传输。存储器布置被设计成使得数据信号可以通过控制器和存储器件之间的数据信号线传送。此外，存储器布置被设计成使得控制信号和地址信号同样能够经由控制器和存储器件之间的数据信号线传送。

2. 发明申请

US20050038966A1 Memory arrangement 失效
标题翻译：内存安排
公开(公告)号：US20050038966A1
公开(公告)日：2005-02-17
申请号：US10850382
申请日：2004-05-21
申请人： Georg Braun , Hermann Ruckerbauer , Maksim Kuzmenka , Siva Raghuram
发明人： Georg Braun , Hermann Ruckerbauer , Maksim Kuzmenka , Siva Raghuram
IPC分类号： G06F13/16 , G11C7/10 , G06F12/00
CPC分类号： G11C7/10 , G06F13/1678
摘要： The present invention relates to a memory arrangement having a controller and having at least one memory device. Data signals, control signals and address signals can be transferred between the controller and the memory device. The memory arrangement is designed in such a way that the data signals can be transferred via data signal lines between the controller and the memory device. The memory arrangement is furthermore designed in such a way that the control signals and the address signals can likewise be transferred via the data signal lines between the controller and the memory device.
摘要翻译：本发明涉及一种具有控制器并具有至少一个存储器件的存储器装置。数据信号，控制信号和地址信号可以在控制器和存储器件之间传输。存储器布置被设计成使得数据信号可以通过控制器和存储器件之间的数据信号线传送。此外，存储器布置被设计成使得控制信号和地址信号同样能够经由控制器和存储器件之间的数据信号线传送。

3. 发明申请

US20070015381A1 Memory module, memory extension memory module, memory module system, and method for manufacturing a memory module 有权
标题翻译：存储器模块，存储器扩展存储器模块，存储器模块系统以及用于制造存储器模块的方法
公开(公告)号：US20070015381A1
公开(公告)日：2007-01-18
申请号：US11481676
申请日：2006-07-06
申请人： Simon Muff , Siva Raghuram
发明人： Simon Muff , Siva Raghuram
IPC分类号： H01R12/00
CPC分类号： G11C5/04 , H05K1/144 , H05K3/366 , H05K2201/045 , H05K2201/10189 , H05K2203/1572
摘要： A memory extension memory module, a memory module system, and a memory module is disclosed. The memory module including at least one memory device and a connector for connecting the memory module to a computer system, wherein the memory module additionally includes a surface-mounted connector for connecting a memory extension memory module to the memory module. Furthermore, a method for manufacturing a memory module is disclosed. The memory module including at least one memory device and at least one connector for connecting a memory extension memory module to the memory module, wherein the at least one memory device and the at least one connector are connected to the memory module in a single manufacturing process.
摘要翻译：公开了一种存储器扩展存储器模块，存储器模块系统和存储器模块。所述存储器模块包括至少一个存储器件和用于将所述存储器模块连接到计算机系统的连接器，其中所述存储器模块还包括用于将存储器扩展存储器模块连接到所述存储器模块的表面安装连接器。此外，公开了一种用于制造存储器模块的方法。所述存储器模块包括至少一个存储器设备和用于将存储器扩展存储器模块连接到所述存储器模块的至少一个连接器，其中所述至少一个存储器设备和所述至少一个连接器在单个制造过程中连接到所述存储器模块。

4. 发明申请

US20060126369A1 Stacked DRAM memory chip for a dual inline memory module (DIMM) 有权
标题翻译：用于双列直插式内存模块（DIMM）的堆叠DRAM内存芯片
公开(公告)号：US20060126369A1
公开(公告)日：2006-06-15
申请号：US11010942
申请日：2004-12-10
申请人： Siva Raghuram
发明人： Siva Raghuram
IPC分类号： G11C5/02
CPC分类号： G11C5/04 , B82Y10/00 , H01L25/0657 , H01L25/18 , H01L2224/48091 , H01L2224/48227 , H01L2225/0651 , H01L2225/06524 , H01L2225/06527 , H01L2924/0102 , H01L2924/01068 , H01L2924/01078 , H01L2924/15311 , H01L2924/00014
摘要： The invention refers to a DRAM Memory Chip for a Dual In Line Memory Module (DIMM) having (a) a predetermined number (M) of stacked DRAM memory dies; (b) wherein each DRAM memory die is selectable by a corresponding memory rank signal (r); (c) wherein each DRAM memory die comprises an array of memory cells; (d) wherein a common internal address bus consisting of address lines is provided for addressing the memory cells and is connected to all M stacked DRAM memory dies; (e) wherein M internal data buses consisting of internal data lines are provided for writing data into the memory cells and reading data out of the memory cells of the stacked DRAM memory dies; wherein (f) an integrated redriving unit is provided which comprises: (f1) buffers for all internal address lines provided for driving external address signals applied to address pads of said DRAM memory chip and; (f2) a multiplexer/demultiplexer which switches the internal data lines of the selected DRAM memory die to data pads of said DRAM memory chip.
摘要翻译：本发明涉及一种用于双列直插存储器模块（DIMM）的DRAM存储器芯片，其具有（a）预定数量（M）个堆叠DRAM存储器管芯; （b）其中每个DRAM存储器管芯可由对应的存储器等级信号（r）选择; （c）其中每个DRAM存储器管芯包括一组存储器单元; （d）其中提供由地址线组成的公共内部地址总线用于寻址存储器单元并连接到所有M个堆叠的DRAM存储器管芯; （e）其中提供由内部数据线组成的M个内部数据总线用于将数据写入存储单元并从堆叠的DRAM存储器管芯的存储单元中读出数据; 其中（f）提供一个集成的重新驱动单元，其包括：（f1）用于驱动施加到所述DRAM存储器芯片的地址焊盘的外部地址信号的所有内部地址线的缓冲器; （f2）多路复用器/解复用器，其将所选DRAM存储器管芯的内部数据线切换到所述DRAM存储器芯片的数据焊盘。

5. 发明申请

US20070258278A1 Memory module and methods for making and using the same 审中-公开
标题翻译：内存模块及其制作和使用方法
公开(公告)号：US20070258278A1
公开(公告)日：2007-11-08
申请号：US11418459
申请日：2006-05-05
申请人： Abdallah Bacha , Rainer Menes , Siva Raghuram
发明人： Abdallah Bacha , Rainer Menes , Siva Raghuram
IPC分类号： G11C5/02
CPC分类号： H05K1/181 , G11C5/04 , G11C8/12 , H05K2201/10159 , H05K2203/1572 , Y02P70/611
摘要： A memory module includes a first printed circuit board, wherein some of the memory chips in each of first and second ranks of memory chips are assembled on one side of the printed circuit board and others of the first and second ranks are assembled on the other side of the printed circuit board. First and second registers are respectively connected to the first and second address buses for respectively addressing the first and second ranks of memory chips. Since the addresses buses are separate for the two ranks, it is possible to activate only the address bus associated with the particular rank being addressed. In this manner, address activation power is saved by not activating the address bus of the other rank which is not addressed. Due to less power dissipation, it is possible to operate the memory module without a full DIMM heat spreader.
摘要翻译：存储器模块包括第一印刷电路板，其中存储器芯片的第一和第二列中的每一个中的一些存储器芯片组装在印刷电路板的一侧上，并且第一和第二列的其它部分被组装在另一侧的印刷电路板。第一和第二寄存器分别连接到第一和第二地址总线，以分别寻址第一和第二等级的存储器芯片。由于地址总线对于两个等级是分开的，所以可以仅激活与被寻址的特定等级相关联的地址总线。以这种方式，通过不激活未被寻址的其他等级的地址总线来节省地址激活功率。由于功耗较小，可以在没有全DIMM散热器的情况下操作内存模块。

6. 发明申请

US20070245072A1 Pre-switching register output signals in registered memory modules 审中-公开
标题翻译：在注册的存储器模块中预切换寄存器输出信号
公开(公告)号：US20070245072A1
公开(公告)日：2007-10-18
申请号：US11384837
申请日：2006-03-21
申请人： Siva Raghuram
发明人： Siva Raghuram
IPC分类号： G06F13/00
CPC分类号： G06F13/4243 , G11C5/00
摘要： Pre-switching of output signals of a register within a registered memory module is described herein. The register receives a plurality of signals at respective input terminals, and the register stores the input signals in response to transitions of a clock signal. The register further includes output terminals on which the stored input signals are present as high or low level output signals. The high and low level output signals of the output terminals are applied to a plurality of memory devices. The high and low level output signals, which are present on the output terminals, are pre-switched to intermediate level signals having a signal height greater than that of the low level output signal and less than that of the high level output signal. The pre-switching occurs between following transitions of the clock signal determined for storing the input signals.
摘要翻译：本文描述了在注册的存储器模块内的寄存器的输出信号的预切换。寄存器在相应的输入端接收多个信号，寄存器响应于时钟信号的转换来存储输入信号。寄存器还包括存储的输入信号作为高电平或低电平输出信号的输出端子。输出端子的高电平和低电平输出信号被施加到多个存储器件。存在于输出端子上的高电平和低电平输出信号被预先切换到具有比低电平输出信号的信号高的信号高度并且小于高电平输出信号的信号高度的中间电平信号。预切换发生在为存储输入信号而确定的时钟信号的以下转换之间。

7. 发明授权

US07266639B2 Memory rank decoder for a multi-rank Dual Inline Memory Module (DIMM) 有权
标题翻译：用于多列双列直插内存模块（DIMM）的内存等级解码器
公开(公告)号：US07266639B2
公开(公告)日：2007-09-04
申请号：US11010182
申请日：2004-12-10
申请人： Siva Raghuram
发明人： Siva Raghuram
IPC分类号： G06F12/00 , G11C8/06 , G11C8/12
CPC分类号： G11C5/04 , G11C8/12
摘要： The invention refers to a Memory Rank Decoder for a Multi-Rank Dual Inline Memory Module (DIMM) having a predetermined number of DRAM memory chips mounted on a printer circuit board (PCB), wherein each DRAM memory chip comprises a predetermined number of stacked DRAM memory dies which are selectable by a memory rank selection signal (r), wherein the memory rank decoder generates the memory rank selection signal (r) in response to external selection signals applied to the dual inline module (DIMM).
摘要翻译：本发明涉及具有安装在打印机电路板（PCB）上的预定数量的DRAM存储器芯片的多级双列直插式存储器模块（DIMM）的存储器级别解码器，其中每个DRAM存储器芯片包括预定数量的堆叠DRAM 可由存储器等级选择信号（r）选择的存储器管芯，其中存储器级解码器响应于施加到双列直插模块（DIMM）的外部选择信号而产生存储器级选择信号（r）。

8. 发明申请

US20070224854A1 Memory module, method of manufacturing a memory module and computer system 审中-公开
标题翻译：内存模块，制造内存模块和计算机系统的方法
公开(公告)号：US20070224854A1
公开(公告)日：2007-09-27
申请号：US11389541
申请日：2006-03-27
申请人： Abdallah Bacha , Siva Raghuram
发明人： Abdallah Bacha , Siva Raghuram
IPC分类号： H05K1/00
CPC分类号： H05K1/144 , H05K1/181 , H05K2201/042 , H05K2201/10159 , H05K2201/10189 , H05K2203/1572
摘要： A memory module includes a first pc-board with a plurality of memory chips assembled thereon and with a second pc-board with a second plurality of memory chips assembled thereon. The first pc-board and the second pc-board are connected via first and second connectors placed on the surfaces of the first and second pc-boards.
摘要翻译：存储器模块包括具有组装在其上的多个存储器芯片的第一印刷电路板和具有组装在其上的第二多个存储器芯片的第二印刷电路板。第一印刷电路板和第二印刷电路板通过放置在第一和第二印刷电路板的表面上的第一和第二连接器连接。

9. 发明申请

US20060129755A1 Memory rank decoder for a Multi-Rank Dual Inline Memory Module (DIMM) 有权
标题翻译：多级双列直插式内存模块（DIMM）的内存等级解码器
公开(公告)号：US20060129755A1
公开(公告)日：2006-06-15
申请号：US11010182
申请日：2004-12-10
申请人： Siva Raghuram
发明人： Siva Raghuram
IPC分类号： G06F12/00
CPC分类号： G11C5/04 , G11C8/12
摘要： The invention refers to a Memory Rank Decoder for a Multi-Rank Dual Inline Memory Module (DIMM) having a predetermined number of DRAM memory chips mounted on a printer circuit board (PCB), wherein each DRAM memory chip comprises a predetermined number of stacked DRAM memory dies which are selectable by a memory rank selection signal (r), wherein the memory rank decoder generates the memory rank selection signal (r) in response to external selection signals applied to the dual inline module (DIMM).
摘要翻译：本发明涉及具有安装在打印机电路板（PCB）上的预定数量的DRAM存储器芯片的多级双列直插式存储器模块（DIMM）的存储器级别解码器，其中每个DRAM存储器芯片包括预定数量的堆叠DRAM 可由存储器等级选择信号（r）选择的存储器管芯，其中存储器级解码器响应于施加到双列直插模块（DIMM）的外部选择信号而产生存储器级选择信号（r）。

10. 发明授权

US07351072B2 Memory module, memory extension memory module, memory module system, and method for manufacturing a memory module 有权
标题翻译：存储器模块，存储器扩展存储器模块，存储器模块系统以及用于制造存储器模块的方法
公开(公告)号：US07351072B2
公开(公告)日：2008-04-01
申请号：US11481676
申请日：2006-07-06
申请人： Simon Muff , Siva Raghuram
发明人： Simon Muff , Siva Raghuram
IPC分类号： H05K1/14
CPC分类号： G11C5/04 , H05K1/144 , H05K3/366 , H05K2201/045 , H05K2201/10189 , H05K2203/1572
摘要： A memory extension memory module, a memory module system, and a memory module is disclosed. The memory module including at least one memory device and a connector for connecting the memory module to a computer system, wherein the memory module additionally includes a surface-mounted connector for connecting a memory extension memory module to the memory module. Furthermore, a method for manufacturing a memory module is disclosed. The memory module including at least one memory device and at least one connector for connecting a memory extension memory module to the memory module, wherein the at least one memory device and the at least one connector are connected to the memory module in a single manufacturing process.
摘要翻译：公开了一种存储器扩展存储器模块，存储器模块系统和存储器模块。所述存储器模块包括至少一个存储器件和用于将所述存储器模块连接到计算机系统的连接器，其中所述存储器模块还包括用于将存储器扩展存储器模块连接到所述存储器模块的表面安装连接器。此外，公开了一种用于制造存储器模块的方法。所述存储器模块包括至少一个存储器设备和用于将存储器扩展存储器模块连接到所述存储器模块的至少一个连接器，其中所述至少一个存储器设备和所述至少一个连接器在单个制造过程中连接到所述存储器模块。

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