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    • 6. 发明申请
    • Method and apparatus for encoding design description in reconfigurable multi-processor system
    • 用于编码可重构多处理器系统中设计描述的方法和装置
    • US20060069739A1
    • 2006-03-30
    • US10538205
    • 2003-12-08
    • Krishnamurthy VaidyanathanGeoffrey Burns
    • Krishnamurthy VaidyanathanGeoffrey Burns
    • G06F15/167
    • G06F9/445G06F15/177G06F15/8023
    • A method (400) and apparatus (100) are disclosed for storing the software specifications (320) for each processor (110) in a multi-processor system (100). The disclosed storage technique reduces the total memory space that is required to store the configuration information for each processor (110) and does not require a linear scaling of the memory size when the number of processors increases. Each unique software specification (320) is stored in memory and a pointer (310) is stored for each processor (110) that identifies the corresponding location in memory (140′) of the configuration information for the processor (110). The size of the memory area that stores the pointers (310) for each processor (110) still has a linear relationship with the number of processors (110). The size of the memory area (140′) that stores the unique software specifications (320) is independent of the number of processors (110).
    • 公开了一种用于在多处理器系统(100)中存储每个处理器(110)的软件规范(320)的方法(400)和装置(100)。 所公开的存储技术减少了存储每个处理器(110)的配置信息所需的总存储空间,并且当处理器数量增加时不需要线性缩放存储器大小。 每个独特的软件规范(320)存储在存储器中,并且为每个处理器(110)存储指示器(310),该处理器识别处理器(110)的配置信息的存储器(140')中的对应位置。 存储每个处理器(110)的指针(310)的存储器区域的大小仍然与处理器(110)的数量呈线性关系。 存储唯一软件规格(320)的存储区域(140')的大小与处理器(110)的数量无关。
    • 7. 发明授权
    • Programmable delay indexed data path register file for array processing
    • 用于阵列处理的可编程延迟索引数据路径寄存器文件
    • US06970895B2
    • 2005-11-29
    • US10026258
    • 2001-12-21
    • Krishnamurthy VaidyanathanGeoffrey Burns
    • Krishnamurthy VaidyanathanGeoffrey Burns
    • G06F9/30G01R1/00G06F9/34G06F9/355G06F12/02G06F15/00G06F15/80G06F17/10G06F17/15
    • G06F9/30098G06F9/3013G06F9/30134
    • A delay addressed data path register file is designed for use in a programmable processor making up a cell in a multi-processor or array signal processing system. The delay addressable register file is particularly useful in, inter alia, adaptive filters where the filter update latency is variable, interpolation filters where the interpolation factor needs to be programmable, and decimation filters where the decimation factor needs to be programmable. The programmability is achieved in an efficient manner, reducing the number of cycles required to perform this task. A single parameter, the “delay limit” value, is programmed at start-up, setting up an internal delay-line within the register file of the processor. Thus, any of the delayed registers can be addressed by specifying the delay index during run-time. The delay line advances one location, modulo “delay-limit”, when the processing loop starts a new iteration.
    • 延迟寻址数据路径寄存器文件被设计用于构成多处理器或阵列信号处理系统中的单元的可编程处理器。 延迟寻址寄存器文件尤其适用于滤波器更新延迟可变的自适应滤波器,内插因子需要可编程的插值滤波器以及抽取因子需要被编程的抽取滤波器。 可编程性以有效的方式实现,减少执行此任务所需的周期数。 在启动时,单个参数“延迟限制”值被编程,在处理器的寄存器文件内设置内部延迟线。 因此,可以通过在运行时指定延迟指数来解决任何延迟寄存器。 当处理循环开始新的迭代时,延迟线前进一个位置,模数“延迟限制”。