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1. 发明授权

US09104403B2 Data processing system having selective redundancy and method therefor 有权
标题翻译：具有选择性冗余的数据处理系统及其方法
公开(公告)号：US09104403B2
公开(公告)日：2015-08-11
申请号：US12858599
申请日：2010-08-18
申请人： Gary R. Morrison , William C. Moyer
发明人： Gary R. Morrison , William C. Moyer
IPC分类号： G06F15/00 , G06F9/30 , G06F9/40 , G06F11/14 , G06F11/16
CPC分类号： G06F9/30145 , G06F11/1405 , G06F11/1479 , G06F11/1497 , G06F11/1629
摘要： A method includes: decoding an instruction a first time to obtain a first decoded instruction; decoding the instruction a second time to obtain a second decoded instruction; comparing at least a portion of the first decoded instruction to at least a portion of the second decoded instruction; and when the at least a portion of the first decoded instruction matches the at least a portion of the second decoded instruction, executing the instruction.
摘要翻译：一种方法包括：第一次解码指令以获得第一解码指令; 第二次对指令进行解码以获得第二解码指令; 将所述第一解码指令的至少一部分与所述第二解码指令的至少一部分进行比较; 并且当所述第一解码指令的至少一部分与所述第二解码指令的所述至少一部分匹配时，执行所述指令。

2. 发明申请

US20120047351A1 DATA PROCESSING SYSTEM HAVING SELECTIVE REDUNDANCY AND METHOD THEREFOR 有权
标题翻译：具有选择性冗余的数据处理系统及其方法
公开(公告)号：US20120047351A1
公开(公告)日：2012-02-23
申请号：US12858599
申请日：2010-08-18
申请人： Gary R. Morrison , William C. Moyer
发明人： Gary R. Morrison , William C. Moyer
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30145 , G06F11/1405 , G06F11/1479 , G06F11/1497 , G06F11/1629
摘要： A method includes: decoding an instruction a first time to obtain a first decoded instruction; decoding the instruction a second time to obtain a second decoded instruction; comparing at least a portion of the first decoded instruction to at least a portion of the second decoded instruction; and when the at least a portion of the first decoded instruction matches the at least a portion of the second decoded instruction, executing the instruction.
摘要翻译：一种方法包括：第一次解码指令以获得第一解码指令; 第二次对指令进行解码以获得第二解码指令; 将所述第一解码指令的至少一部分与所述第二解码指令的至少一部分进行比较; 并且当所述第一解码指令的至少一部分与所述第二解码指令的所述至少一部分匹配时，执行所述指令。

3. 发明授权

US07444568B2 Method and apparatus for testing a data processing system 失效
标题翻译：用于测试数据处理系统的方法和装置
公开(公告)号：US07444568B2
公开(公告)日：2008-10-28
申请号：US11355681
申请日：2006-02-16
申请人： Gary R. Morrison , Jose A. Lyon , William C. Moyer , Anthony M. Reipold
发明人： Gary R. Morrison , Jose A. Lyon , William C. Moyer , Anthony M. Reipold
IPC分类号： G01R31/28
CPC分类号： G01R31/318544 , G01R31/318536 , G01R31/318552 , G06F11/2236
摘要： A method for testing at least one logic block of a processor includes, during execution of a user application by the processor, the processor generating a stop and test indicator. In response to the generation of the stop and test indicator, stopping the execution of the user application and, if necessary, saving a state of the at least one logic block of the processor. The method further includes applying a test stimulus for testing the at least one logic block of the processor. The test stimulus may be shifted into scan chains so as to perform scan testing of the processor during normal operation, such as during execution of a user application.
摘要翻译：用于测试处理器的至少一个逻辑块的方法包括在处理器执行用户应用期间，处理器产生停止和测试指示符。响应于产生停止和测试指示符，停止执行用户应用程序，并且如果需要，保存处理器的至少一个逻辑块的状态。该方法还包括应用用于测试处理器的至少一个逻辑块的测试激励。测试刺激可以被转移到扫描链中，以便在正常操作期间，例如在用户应用的执行期间执行处理器的扫描测试。

4. 发明授权

US09361104B2 Systems and methods for determining instruction execution error by comparing an operand of a reference instruction to a result of a subsequent cross-check instruction 有权
标题翻译：通过将参考指令的操作数与随后的交叉检查指令的结果进行比较来确定指令执行错误的系统和方法
公开(公告)号：US09361104B2
公开(公告)日：2016-06-07
申请号：US12856430
申请日：2010-08-13
申请人： Gary R. Morrison , William C. Moyer
发明人： Gary R. Morrison , William C. Moyer
IPC分类号： G06F11/14 , G06F9/30 , G06F9/38 , G06F11/07
CPC分类号： G06F9/30076 , G06F9/3826 , G06F11/0721 , G06F11/0751 , G06F11/1479
摘要： In a data processing system having execution circuitry, a method includes providing a cross-check instruction and a reference instruction to the execution circuitry, where the reference instruction has an operand. The method also includes executing the reference instruction to obtain a first result. Residual information is derived from execution of the reference instruction, and the method also includes executing the cross-check instruction using the residual information to obtain a second result. The second result obtained from execution of the cross-check instruction is compared to the operand of the reference instruction to determine whether an error occurred during execution of the reference instruction or the cross-check instruction.
摘要翻译：在具有执行电路的数据处理系统中，一种方法包括向执行电路提供交叉检查指令和参考指令，其中参考指令具有操作数。该方法还包括执行参考指令以获得第一结果。从执行参考指令导出剩余信息，并且该方法还包括使用剩余信息执行交叉检查指令以获得第二结果。从执行交叉检查指令获得的第二结果与参考指令的操作数进行比较，以确定执行参考指令或交叉检查指令期间是否发生错误。

5. 发明授权

US10031773B2 Method to communicate task context information and device therefor 有权
公开(公告)号：US10031773B2
公开(公告)日：2018-07-24
申请号：US14185005
申请日：2014-02-20
申请人： William C. Moyer
发明人： William C. Moyer
IPC分类号： G06F9/48
摘要： Task context information is transferred concurrently from a processor core to an accelerator and to a context memory. The accelerator performs an operation based on the task context information and the context memory saves the task context information. The order of transfer between the processor core is based upon a programmable indicator. During a context restore operation information is concurrently provided to data bus from both the accelerator and the processor core.

6. 发明授权

US09372723B2 System and method for conditional task switching during ordering scope transitions 有权
标题翻译：在订购范围转换期间进行条件任务切换的系统和方法
公开(公告)号：US09372723B2
公开(公告)日：2016-06-21
申请号：US14231784
申请日：2014-04-01
申请人： Zheng Xu , Tommi M. Jokinen , William C. Moyer
发明人： Zheng Xu , Tommi M. Jokinen , William C. Moyer
IPC分类号： G06F9/48
CPC分类号： G06F9/4843 , G06F9/461 , G06F9/48
摘要： A data processing system includes a processor core and ordering scope manager circuitry. The processor core sends an indication of a first ordering scope identifier for a current ordering scope a task currently being executed by the processor core and a second ordering scope identifier for a next-in-order ordering scope of the task. The ordering scope manager receives the indication the first and second ordering scope identifiers from processor core, and, provides a no task switch indicator to the processor core in response to determining that the first task is a first-in-transition-order task for the first ordering scope identifier and that processor core is authorized to execute the next-in-order ordering scope. The processor core transitions from executing in the current ordering scope to executing in the next-in-order ordering scope without performing task switch in response to the no task switch indicator being provided.
摘要翻译：数据处理系统包括处理器核心和订购范围管理器电路。处理器核心向当前订购范围发送当前由处理器核心执行的任务的第一订购范围标识符和用于任务的下一个订购范围的第二订购范围标识符的指示。订购范围管理器从处理器核心接收第一和第二订购范围标识符的指示，并且响应于确定第一任务是第一个转换顺序任务，向处理器核心提供无任务切换指示符第一个订购范围标识符，该处理器核心被授权执行下一个订购范围。处理器核心从当前订购范围内的执行转变为按顺序排序范围执行，而不响应于提供无任务切换指示器而执行任务切换。

7. 发明申请

US20160098313A1 WATCHDOG METHOD AND DEVICE 审中-公开
标题翻译：手表方法和装置
公开(公告)号：US20160098313A1
公开(公告)日：2016-04-07
申请号：US14504702
申请日：2014-10-02
申请人： William C. Moyer
发明人： William C. Moyer
IPC分类号： G06F11/07 , G06F9/50
CPC分类号： G06F11/0757 , G06F11/0724
摘要： Each task assigned to a core can be considered an “active” task. Sequential strobe signals of a watchdog signal can be spaced apart in time by a certain duration. The duration between strobe signals is longer than the expected duration of an active task. By knowing that all tasks being monitored are expected to execute within an expected amount of time, the duration between the strobe signals can be set to be longer than that expected amount of time. If a task has not transitioned to inactive by a next strobe, a watchdog error has occurred.
摘要翻译：分配给核心的每个任务可以被认为是一个“主动”任务。看门狗信号的顺序选通信号可以在时间上间隔一段持续时间。选通信号之间的持续时间长于活动任务的预期持续时间。通过知道所有被监视的任务预期在预期的时间内执行，选通信号之间的持续时间可以被设置为比预期的时间长。如果任务没有被下一个选通转换为非活动状态，则发生看门狗错误。

8. 发明授权

US09268527B2 Method and device for generating an exception 有权
标题翻译：用于产生异常的方法和设备
公开(公告)号：US09268527B2
公开(公告)日：2016-02-23
申请号：US13841630
申请日：2013-03-15
申请人： William C. Moyer
发明人： William C. Moyer
IPC分类号： G06F7/483 , G06F7/499
CPC分类号： G06F7/483 , G06F7/49905
摘要： A floating point value can represent a number or something that is not a number (NaN). A floating point value that is a NaN having data field that stores information, such as a propagation count that indicates the number of times a NaN value has been propagated through instructions. A NaN evaluation instruction can determine whether one or more operands is a NaN operand of a particular type, and if so can generate a result that is a NaN of a different type. An exception can be generated based upon the NaN of the different type being provided as a resultant.
摘要翻译：浮点值可以表示数字或不是数字（NaN）的数据。具有存储信息的数据字段的NaN的浮点值，例如表示通过指令传播NaN值的次数的传播计数。 NaN评估指令可以确定一个或多个操作数是否是特定类型的NaN操作数，如果可以生成作为不同类型的NaN的结果。可以基于作为结果提供的不同类型的NaN产生异常。

9. 发明申请

US20150277973A1 SYSTEM AND METHOD FOR CONDITIONAL TASK SWITCHING DURING ORDERING SCOPE TRANSITIONS 有权
标题翻译：系统和方法在订单范围转换期间进行条件性的任务切换
公开(公告)号：US20150277973A1
公开(公告)日：2015-10-01
申请号：US14231789
申请日：2014-04-01
申请人： Zheng Xu , Tommi M. Jokinen , William C. Moyer
发明人： Zheng Xu , Tommi M. Jokinen , William C. Moyer
IPC分类号： G06F9/48
CPC分类号： G06F9/4843 , G06F9/461 , G06F9/48
摘要： A data processing system includes a processor core and a hardware module. The processor core performs tasks on data packets. The hardware module stores a first ordering scope identifier at a first storage location of the ordering scope manager. The first ordering scope identifier indicates a first ordering scope that a first task is operating in. The ordering scope manager increments the first ordering scope identifier to create a new ordering scope identifier. In response to determining that the processor core is authorized to transition the first task from the first ordering scope to a second ordering scope associated with the new ordering scope identifier, the ordering scope manager provides hint information to the processor core. The processor core transitions from the first ordering scope to the second ordering scope without completing a task switch in response to the hint information.
摘要翻译：数据处理系统包括处理器核心和硬件模块。处理器内核在数据包上执行任务。硬件模块在订购范围管理器的第一存储位置处存储第一订购范围标识符。第一个订购范围标识符指示第一个任务正在操作的第一个订购范围。订购范围管理器增加第一个订购范围标识符以创建新的订购范围标识符。响应于确定处理器核被授权将第一任务从第一排序范围转换到与新排序范围标识符相关联的第二排序范围，订购范围管理器向处理器核提供提示信息。处理器核心从第一订购范围转换到第二订购范围，而不响应于提示信息完成任务切换。

10. 发明授权

US08739165B2 Shared resource based thread scheduling with affinity and/or selectable criteria 有权
标题翻译：基于共享资源的线程调度，具有亲和度和/或可选择的标准
公开(公告)号：US08739165B2
公开(公告)日：2014-05-27
申请号：US12017988
申请日：2008-01-22
申请人： Andrew C. Russell , William C. Moyer
发明人： Andrew C. Russell , William C. Moyer
IPC分类号： G06F9/46
CPC分类号： G06F9/5027 , G06F9/5094 , Y02D10/22
摘要： Threads may be scheduled to be executed by one or more cores depending upon whether it is more desirable to minimize power or to maximize performance. If minimum power is desired, threads may be schedule so that the active devices are most shared; this will minimize the number of active devices at the expense of performance. On the other hand, if maximum performance is desired, threads may be scheduled so that active devices are least shared. As a result, threads will have more active devices to themselves, resulting in greater performance at the expense of additional power consumption. Thread affinity with a core may also be taken into consideration when scheduling threads in order to improve the power consumption and/or performance of an apparatus.
摘要翻译：线程可以被调度为由一个或多个核执行，这取决于是否更希望最小化功率或最大化性能。如果需要最小功率，则可以调度线程，使得有效设备是最共享的; 这将以牺牲性能为代价来最小化活动设备的数量。另一方面，如果需要最大性能，则可以调度线程，使得有源设备最不共享。因此，线程将自己拥有更多的活动设备，导致更高的性能，而牺牲额外的功耗。为了提高设备的功耗和/或性能，调度线程时也可以考虑与核心的线程亲和度。

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