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1. 发明授权

US5959994A ATM/SONET network enhanced as a universal computer system interconnect 失效
标题翻译： ATM / SONET网络作为通用计算机系统互联增强
公开(公告)号：US5959994A
公开(公告)日：1999-09-28
申请号：US699260
申请日：1996-08-19
申请人： Gary Lee Boggs , Robert Samuel Cooper , Gene Robert Erickson , Douglas Edward Hundley , Gregory H. Milby , P. Keith Muller , Curtis Hall Stehley , Donald G. Tipon
发明人： Gary Lee Boggs , Robert Samuel Cooper , Gene Robert Erickson , Douglas Edward Hundley , Gregory H. Milby , P. Keith Muller , Curtis Hall Stehley , Donald G. Tipon
IPC分类号： H04L12/56 , H04Q11/04
CPC分类号： H04L49/3081 , H04L49/30 , H04Q11/0478 , H04L2012/5652 , H04L49/20 , Y10S370/905 , Y10S370/907
摘要： An enhanced ATM switch with CPU node interconnect functionality and peripheral interconnect functionality and network functionality. The ATM switch provides low latency transfer between computer nodes and performs input/output operations with peripherals through the ATM network. SCSI Fibre Channel protocol (FCP) commands are implemented according to ATM standards to provide communication with peripherals. A segmentation and reassembly (SAR) unit is provided for performing ATM segmentation and reassembly. The SAR includes functional units which allow direct connection of an application agent to the core of the switch once the cell characteristics are determined by the application agent and provides ATM cell translation to and from available kernel buffers. The transmission media in the ATM network comprises digital optical links. The enhanced ATM switch may also include a synchronous optical network (SONET) interface for providing SONET transmission over the digital optical links in the ATM network.
摘要翻译：具有CPU节点互连功能和外设互连功能和网络功能的增强型ATM交换机。 ATM交换机在计算机节点之间提供低延迟传输，并通过ATM网络与外设进行输入/输出操作。 SCSI光纤通道协议（FCP）命令根据ATM标准实现，以提供与外设的通信。提供了分段和重组（SAR）单元，用于执行ATM分段和重组。一旦特征由应用代理确定并且向可用的内核缓冲器提供ATM信元转换，则SAR包括功能单元，其允许应用代理直接连接到交换机的核心。 ATM网络中的传输媒体包括数字光链路。增强型ATM交换机还可以包括用于在ATM网络中的数字光链路上提供SONET传输的同步光网络（SONET）接口。

2. 发明申请

US20080244126A1 METHOD AND APPARATUS FOR CHAINING MULTIPLE INDEPENDENT HARDWARE ACCELERATION OPERATIONS 有权
标题翻译：用于链接多个独立硬件加速操作的方法和装置
公开(公告)号：US20080244126A1
公开(公告)日：2008-10-02
申请号：US12135809
申请日：2008-06-09
申请人： Douglas Edward Hundley
发明人： Douglas Edward Hundley
IPC分类号： G06F13/00
CPC分类号： G06F9/4843
摘要： Multiple hardware accelerators can be used to efficiently perform processes that would otherwise be performed by general purpose hardware running software. The software overhead and bus bandwidth associated with running multiple hardware acceleration processes can be reduced by chaining multiple independent hardware acceleration operations within a circuit card assembly. Multiple independent hardware accelerators can be configured on a single circuit card assembly that is coupled to a computing device. The computing device can generate a playlist of hardware acceleration operations identifying hardware accelerators and associated accelerator options. A task management unit on the circuit card assembly receives the playlist and schedules the hardware acceleration operations such that multiple acceleration operations may be successively chained together without intervening data exchanges with the computing device.
摘要翻译：可以使用多个硬件加速器来有效地执行否则将由通用硬件运行软件执行的进程。通过连接电路卡组件内的多个独立硬件加速操作可以减少与运行多个硬件加速过程相关的软件开销和总线带宽。可以在耦合到计算设备的单个电路卡组件上配置多个独立的硬件加速器。计算设备可以生成识别硬件加速器和相关联的加速器选项的硬件加速操作的播放列表。电路卡组件上的任务管理单元接收播放列表并调度硬件加速操作，使得可以将多个加速操作连续地链接在一起，而无需与计算设备进行数据交换。

3. 发明授权

US07430652B2 Devices for performing multiple independent hardware acceleration operations and methods for performing same 失效
标题翻译：用于执行多个独立硬件加速操作的设备和执行相同操作的方法
公开(公告)号：US07430652B2
公开(公告)日：2008-09-30
申请号：US10403419
申请日：2003-03-28
申请人： Douglas Edward Hundley
发明人： Douglas Edward Hundley
IPC分类号： G06F15/00 , G06F15/76
CPC分类号： G06F9/4843
摘要： Multiple hardware accelerators can be used to efficiently perform processes that would otherwise be performed by general purpose hardware running software. The software overhead and bus bandwidth associated with running multiple hardware acceleration processes can be reduced by chaining multiple independent hardware acceleration operations within a circuit card assembly. Multiple independent hardware accelerators can be configured on a single circuit card assembly that is coupled to a computing device. The computing device can generate a playlist of hardware acceleration operations identifying hardware accelerators and associated accelerator options. A task management unit on the circuit card assembly receives the playlist and schedules the hardware acceleration operations such that multiple acceleration operations may be successively chained together without intervening data exchanges with the computing device.
摘要翻译：可以使用多个硬件加速器来有效地执行否则将由通用硬件运行软件执行的进程。通过连接电路卡组件内的多个独立硬件加速操作可以减少与运行多个硬件加速过程相关的软件开销和总线带宽。可以在耦合到计算设备的单个电路卡组件上配置多个独立的硬件加速器。计算设备可以生成识别硬件加速器和相关联的加速器选项的硬件加速操作的播放列表。电路卡组件上的任务管理单元接收播放列表并调度硬件加速操作，使得可以将多个加速操作连续地链接在一起，而无需与计算设备进行数据交换。

4. 发明授权

US07925863B2 Hardware device comprising multiple accelerators for performing multiple independent hardware acceleration operations 有权
标题翻译：包括用于执行多个独立硬件加速操作的多个加速器的硬件设备
公开(公告)号：US07925863B2
公开(公告)日：2011-04-12
申请号：US12135809
申请日：2008-06-09
申请人： Douglas Edward Hundley
发明人： Douglas Edward Hundley
IPC分类号： G06F15/00 , G06F15/76 , G06F9/46
CPC分类号： G06F9/4843
摘要： Multiple hardware accelerators can be used to efficiently perform processes that would otherwise be performed by general purpose hardware running software. The software overhead and bus bandwidth associated with running multiple hardware acceleration processes can be reduced by chaining multiple independent hardware acceleration operations within a circuit card assembly. Multiple independent hardware accelerators can be configured on a single circuit card assembly that is coupled to a computing device. The computing device can generate a playlist of hardware acceleration operations identifying hardware accelerators and associated accelerator options. A task management unit on the circuit card assembly receives the playlist and schedules the hardware acceleration operations such that multiple acceleration operations may be successively chained together without intervening data exchanges with the computing device.
摘要翻译：可以使用多个硬件加速器来有效地执行否则将由通用硬件运行软件执行的进程。通过连接电路卡组件内的多个独立硬件加速操作可以减少与运行多个硬件加速过程相关的软件开销和总线带宽。可以在耦合到计算设备的单个电路卡组件上配置多个独立的硬件加速器。计算设备可以生成识别硬件加速器和相关联的加速器选项的硬件加速操作的播放列表。电路卡组件上的任务管理单元接收播放列表并调度硬件加速操作，使得可以将多个加速操作连续地链接在一起，而无需与计算设备进行数据交换。

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