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1. 发明授权

US09628906B2 Method and electrical interface circuit enabling multiplexing 有权
公开(公告)号：US09628906B2
公开(公告)日：2017-04-18
申请号：US13995365
申请日：2012-02-09
申请人： Gajendranath Chowdary , Ravpreet Singh , Shyam Somayajula
发明人： Gajendranath Chowdary , Ravpreet Singh , Shyam Somayajula
IPC分类号： H01H47/00 , H01H83/00 , H02J7/00 , H04R3/00
CPC分类号： H04R3/00 , H02J7/0042 , H02J7/0055 , H04R2410/00 , Y10T307/858
摘要： An electrical interface circuit includes a microphone circuit, a battery charger circuit and an electrical connector for connecting the electrical interface circuit to an external device. The electrical connector has a pin on which signals are multiplexed for connecting either the battery charger circuit to an external supply voltage, or the microphone circuit to an external microphone. The battery charger circuit includes an amplifying circuit for controlling voltage or current to a battery at battery charging, and a p-type power transistor. The pin is connected to the microphone circuit and to a source of the p-type power transistor. When a voltage applied to the pin exceeds the battery voltage, the p-type power transistor provides current from the pin to the charger circuit, and, otherwise, the charger circuit and battery are disconnected from the pin. A method of multiplexing signals on the electrical interface circuit is also disclosed.

2. 发明申请

US20120306502A1 Circuit for Controlling Current to Light-Emitting Diode (LED) 有权
标题翻译：用于控制发光二极管（LED）电流的电路
公开(公告)号：US20120306502A1
公开(公告)日：2012-12-06
申请号：US13516578
申请日：2010-12-10
申请人： Shyam Somayajula , Nageswara Rao Nalam
发明人： Shyam Somayajula , Nageswara Rao Nalam
IPC分类号： G01R31/44 , G01R31/26
CPC分类号： G01R31/024 , G01R31/2635 , H05B33/0893
摘要： The present invention discloses a current controlling circuit wherein the circuit (200) comprises a DC power source (202), an inductor (204), a N-channel Metal Oxide Semiconductor (NMOS) (206), one or more LEDs (208) connected in series, a first resistor (Rsense) and a switching arrangement (210). The positive terminal of the DC power source (202) is connected to the inductor (204) in series. The series of LED (208) is connected in series with the inductor (204) and the first resistor (Rsense). According to an embodiment the switching arrangement (210) comprises a second resistor (Rslt), a first switch (212) and a second switch (214). The second resistor (Rslt) is connected in series with the second switch (214) and connected in parallel with the first switch (212). The switching arrangement (210) is connected in series with the first resistor (Rsense) and the negative terminal of the DC supply (202).
摘要翻译：本发明公开了一种电流控制电路，其中电路（200）包括直流电源（202），电感器（204），N沟道金属氧化物半导体（NMOS）（206），一个或多个LED（208）串联连接，第一电阻（Rsense）和开关装置（210）。直流电源（202）的正极端子与电感器（204）串联连接。 LED（208）系列与电感器（204）和第一电阻器（Rsense）串联连接。根据实施例，开关装置（210）包括第二电阻器（Rslt），第一开关（212）和第二开关（214）。第二电阻器（Rslt）与第二开关（214）串联连接并与第一开关（212）并联连接。开关装置（210）与DC电源（202）的第一电阻（Rsense）和负极端子串联连接。

3. 发明授权

US07324162B2 Method and apparatus to improve ADC dynamic range in a video decoder 有权
标题翻译：提高视频解码器中ADC动态范围的方法和装置
公开(公告)号：US07324162B2
公开(公告)日：2008-01-29
申请号：US10964550
申请日：2004-10-13
申请人： Daniel Gudmondson , Shyam Somayajula
发明人： Daniel Gudmondson , Shyam Somayajula
IPC分类号： H03M1/12
CPC分类号： H04N5/18 , H03M1/129
摘要： A video decoder in which 1) resolution quality can be improved for a given bit count analog-to-digital converter, 2) a lower bit count analog-to-digital converter can be used with substantially similar quality or 3) a combination of improved resolution quality with a lower bit count analog-to-digital converter can be done. In the preferred embodiment, a DC bias is added to the video signal after the sync portion of the composite signal has been received and prior to the active video being received. This bias is then removed after the end of the active video period. By applying this bias, the DC voltage level of the video signals is actually reduced, so that the full scale value of the analog-to-digital conversion process can also be reduced. Thus, compared to using an unbiased signal, increased A/D converter resolution is obtained. In an alternative embodiment, the sync portion can be biased upwardly during the front porch and then be returned during the back porch.
摘要翻译：一种视频解码器，其中1）对于给定位计数模数转换器可以改进分辨率质量，2）可以使用具有基本相似质量的较低位计数模数转换器，或3）改进的组合可以进行低位数模数转换器的分辨率质量。在优选实施例中，在已经接收到合成信号的同步部分之后并且在接收到活动视频之前，将DC偏压添加到视频信号。然后在活动视频周期结束后删除该偏置。通过施加该偏压，视频信号的直流电压电平实际上被减小，从而也可以减小模数转换处理的满量程值。因此，与使用无偏信号相比，获得了增加的A / D转换器分辨率。在替代实施例中，同步部分可以在前部门口向上偏置，然后在后廊期间返回。

4. 发明授权

US08912798B2 Circuit for controlling current to light-emitting diode (LED) 有权
标题翻译：用于控制电流至发光二极管（LED）的电路
公开(公告)号：US08912798B2
公开(公告)日：2014-12-16
申请号：US13516578
申请日：2010-12-10
申请人： Shyam Somayajula , Nageswara Nalam , Arnold James Dsouza , Ankit Seedher
发明人： Shyam Somayajula , Nageswara Nalam , Arnold James Dsouza , Ankit Seedher
IPC分类号： G01R31/00 , G01R31/02 , H05B33/08 , G01R31/26
CPC分类号： G01R31/024 , G01R31/2635 , H05B33/0893
摘要： A current controlling circuit comprises a DC power source, an inductor, a N-channel Metal Oxide Semiconductor (NMOS), one or more LEDs connected in series, a first resistor and a switching arrangement. The positive terminal of the DC power source is connected to the inductor in series. The series of LED is connected in series with the inductor and the first resistor. According to an embodiment the switching arrangement comprises a second resistor, a first switch and a second switch. The second resistor is connected in series with the second switch and connected in parallel with the first switch. The switching arrangement is connected in series with the first resistor and the negative terminal of the DC supply.
摘要翻译：电流控制电路包括直流电源，电感器，N沟道金属氧化物半导体（NMOS），串联连接的一个或多个LED，第一电阻器和开关装置。直流电源的正极端子与电感器串联连接。该系列LED与电感和第一个电阻串联。根据实施例，开关装置包括第二电阻器，第一开关和第二开关。第二电阻器与第二开关串联连接并与第一开关并联连接。开关装置与DC电源的第一电阻器和负极端子串联。

5. 发明授权

US08787597B2 Pop-up noise suppression in audio 有权
标题翻译：音频中的弹出式噪声抑制
公开(公告)号：US08787597B2
公开(公告)日：2014-07-22
申请号：US12713078
申请日：2010-02-25
申请人： Sanjeev Ranganathan , Shyam Somayajula , Srinath Sridharan , Lionel Cimaz
发明人： Sanjeev Ranganathan , Shyam Somayajula , Srinath Sridharan , Lionel Cimaz
IPC分类号： H04R3/00
CPC分类号： H04R3/002 , G10K11/002 , H04R3/00 , H04R3/007
摘要： Systems and methods for suppressing pop-up noise in an audio signal are disclosed. The system includes a driver circuit shared by a pin interface and a complementary pin interface. A control unit is coupled to the pin interface and the complementary pin interface. To activate the pin interface, the control unit is configured to first activate the driver output at the complementary pin interface. Once the complementary pin interface achieves a preset voltage, the driver output is switched to the pin interface by the control unit. In addition, the driver circuit can be calibrated for a DC offset on the complementary pin interface by re-using calibration data calculated at the pin interface. Further, DC correction signals can be provided from a pre-biasing circuit based on the calibration data of the driver circuit.
摘要翻译：公开了用于抑制音频信号中的弹出噪声的系统和方法。该系统包括由引脚接口和互补引脚接口共享的驱动器电路。控制单元耦合到引脚接口和互补引脚接口。要激活引脚接口，控制单元配置为首先在互补引脚接口处激活驱动器输出。一旦互补引脚接口达到预设电压，驱动器输出就由控制单元切换到引脚接口。此外，可以通过重新使用在引脚接口处计算出的校准数据，在互补引脚接口上校准驱动器电路的直流偏移。此外，可以基于驱动器电路的校准数据从预偏置电路提供直流校正信号。

6. 发明申请

US20070188358A1 METHOD AND SYSTEM FOR SAMPLING A SIGNAL 失效
标题翻译：采样信号的方法和系统
公开(公告)号：US20070188358A1
公开(公告)日：2007-08-16
申请号：US11738745
申请日：2007-04-23
申请人： Shyam Somayajula
发明人： Shyam Somayajula
IPC分类号： H03M7/34
CPC分类号： H03M1/0658 , H03M1/0818 , H03M1/1215 , H03M1/128 , H03M3/336 , H03M3/458 , H03M3/47
摘要： A system includes a digital circuit that may be clocked by a digital clock signal having an associated clock period. The system also includes a sample clock generation circuit coupled to a sampling circuit. The sample clock generation circuit may be configured to receive an input clock having a fixed phase relationship with respect to the digital clock signal. The sample clock generation circuit may also generate a sample clock having a first sampling edge corresponding to a first relative offset within the clock period and a subsequent sampling edge corresponding to a different relative offset within the clock period. The sampling circuit may be configured to sample a designated signal upon a first sampling instance corresponding to the first sampling edge and to sample the designated signal upon a subsequent sampling instance corresponding to the subsequent sampling edge.
摘要翻译：一种系统包括可由具有相关时钟周期的数字时钟信号来计时的数字电路。该系统还包括耦合到采样电路的采样时钟产生电路。采样时钟产生电路可以被配置为接收相对于数字时钟信号具有固定相位关系的输入时钟。采样时钟产生电路还可以产生具有与时钟周期内的第一相对偏移相对应的第一采样边沿和对应于时钟周期内的不同相对偏移的后续采样边沿的采样时钟。采样电路可以被配置为在对应于第一采样边缘的第一采样实例上对指定信号进行采样，并且在对应于后续采样边沿的后续采样实例上采样指定信号。

7. 发明申请

US20060077303A1 Method and apparatus to improve ADC dynamic range in a video decoder 有权
标题翻译：提高视频解码器中ADC动态范围的方法和装置
公开(公告)号：US20060077303A1
公开(公告)日：2006-04-13
申请号：US10964550
申请日：2004-10-13
申请人： Daniel Gudmundson , Shyam Somayajula
发明人： Daniel Gudmundson , Shyam Somayajula
IPC分类号： H03M1/12
CPC分类号： H04N5/18 , H03M1/129
摘要： A video decoder in which 1) resolution quality can be improved for a given bit count analog-to-digital converter, 2) a lower bit count analog-to-digital converter can be used with substantially similar quality or 3) a combination of improved resolution quality with a lower bit count analog-to-digital converter can be done. In the preferred embodiment, a DC bias is added to the video signal after the sync portion of the composite signal has been received and prior to the active video being received. This bias is then removed after the end of the active video period. By applying this bias, the DC voltage level of the video signals is actually reduced, so that the full scale value of the analog-to-digital conversion process can also be reduced. Thus, compared to using an unbiased signal, increased A/D converter resolution is obtained. In an alternative embodiment, the sync portion can be biased upwardly during the front porch and then be returned during the back porch.
摘要翻译：一种视频解码器，其中1）对于给定位计数模数转换器可以改进分辨率质量，2）可以使用具有基本相似质量的较低位计数模数转换器，或3）改进的组合可以进行低位数模数转换器的分辨率质量。在优选实施例中，在已经接收到合成信号的同步部分之后并且在接收到活动视频之前，将DC偏压添加到视频信号。然后在活动视频周期结束后删除该偏置。通过施加该偏压，视频信号的直流电压电平实际上被减小，从而也可以减小模数转换处理的满量程值。因此，与使用无偏信号相比，获得了增加的A / D转换器分辨率。在替代实施例中，同步部分可以在前部门口向上偏置，然后在后廊期间返回。

8. 发明授权

US09172303B2 Power management unit systems and methods 有权
标题翻译：电源管理单元系统和方法
公开(公告)号：US09172303B2
公开(公告)日：2015-10-27
申请号：US13048100
申请日：2011-03-15
申请人： Sriharsha Vasadi , Ankit Seedher , Shyam Somayajula
发明人： Sriharsha Vasadi , Ankit Seedher , Shyam Somayajula
IPC分类号： G05F1/00 , H02M3/158 , H02M1/00
CPC分类号： H02M3/158 , H02M2001/009 , Y10T307/406
摘要： Systems and methods provide for a power management unit and its operation. The power management unit includes: a step-down power converter configured to receive a first voltage and output a second voltage, wherein the second voltage is less than the first voltage and at least one step-up power converter configured to receive the second voltage and output a third voltage, wherein the third voltage is greater than the second voltage. It also includes an inductive element connected to the step-down power converter and the at least one step-up power converter and configured to store energy and selectively release the stored energy, wherein the inductive element is time shared by both the step-down power converter and the at least one step-up power converter; and a finite state machine configured to control the time sharing of the inductive element.
摘要翻译：系统和方法提供电源管理单元及其操作。电源管理单元包括：降压功率转换器，被配置为接收第一电压并输出第二电压，其中第二电压小于第一电压，并且至少一个升压功率转换器被配置为接收第二电压，以及输出第三电压，其中第三电压大于第二电压。它还包括连接到降压功率转换器和至少一个升压功率转换器并且被配置为存储能量并选择性地释放所存储的能量的感应元件，其中电感元件由降压功率转换器和至少一个升压功率转换器; 以及被配置为控制电感元件的时间共享的有限状态机。

9. 发明申请

US20120313695A1 High Voltage Tolerant Inverting Charge Pump 有权
标题翻译：高耐压反相电荷泵
公开(公告)号：US20120313695A1
公开(公告)日：2012-12-13
申请号：US13515233
申请日：2010-12-10
申请人： J. Raja Prabhu , Shyam Somayajula
发明人： J. Raja Prabhu , Shyam Somayajula
IPC分类号： G05F1/10
CPC分类号： H02M3/07 , H02M2003/071
摘要： The present invention provides a high voltage tolerant regulated inverting charge pump circuit utilizing low-voltage semiconductor devices, capable of operation directly from a high voltage source. The circuit according to the present invention comprises a plurality of high voltage tolerant pre-driver circuits, connected to the high voltage source, for driving the charge pump low voltage switching devices appropriately for reliable operation. A flying capacitive element connected to the high voltage source through a plurality of low voltage semiconductor devices acting as a switch, peak current limiter, and cascode device. An output capacitive element connected to the flying capacitive element through a plurality of low voltage semi-conductor devices acting as a switch, peak current limiter, regulating element and cascode device. Further, the circuit of the present invention comprises a negative feedback controller connected to the output capacitor to regulate the output voltage over a wide range of load current.
摘要翻译：本发明提供一种利用低压半导体器件的高耐压调节反相电荷泵电路，能够直接从高压源工作。根据本发明的电路包括连接到高电压源的多个高耐压预驱动器电路，用于适当地驱动电荷泵低压开关器件以进行可靠的操作。通过用作开关的多个低电压半导体器件，峰值电流限制器和共源共栅器件，连接到高电压源的浮动电容元件。输出电容元件通过多个用作开关的低电压半导体器件，峰值电流限制器，调节元件和共源共栅器件连接到飞行电容元件。此外，本发明的电路包括连接到输出电容器的负反馈控制器，以在宽的负载电流范围内调节输出电压。

10. 发明授权

US07400362B1 Method and apparatus to interface video signals to a decoder to compensate for droop 有权
标题翻译：将视频信号连接到解码器以补偿下垂的方法和装置
公开(公告)号：US07400362B1
公开(公告)日：2008-07-15
申请号：US11015756
申请日：2004-12-16
申请人： Daniel Gudmundson , Shyam Somayajula , Ahsan Habib Chowdhury , James A. Antone , Rahul Singh
发明人： Daniel Gudmundson , Shyam Somayajula , Ahsan Habib Chowdhury , James A. Antone , Rahul Singh
IPC分类号： H04N7/01 , G05F1/40
CPC分类号： H04N5/21
摘要： A system in which drooping of the video levels due to leakage currents and proper DC bias level is addressed by providing a charge into the video signal to offset the leakage currents and to provide DC bias. To determine the leakage current level, measurements are made measuring the voltages of the syncs and the blanking intervals. To determine the DC bias, a measurement is made of the sync. Over a series of video lines these measurements are averaged. If the average is below the desired level, a charge is provided via a current source to the incoming signal. By having the current source provide charge during each video line, droop is reduced and the proper DC bias is provided.
摘要翻译：通过向视频信号中提供电荷来补偿泄漏电流并提供DC偏压来解决由泄漏电流和适当的DC偏置电平引起的视频电平下降的系统。为了确定泄漏电流电平，可以测量同步电压和消隐间隔。为了确定直流偏置，测量同步。通过一系列视频线对这些测量进行平均。如果平均值低于所需的电平，则通过电流源向输入信号提供电荷。通过使电流源在每个视频行期间提供电荷，降低下降并提供适当的DC偏压。

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