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1. 发明授权

US06943125B2 Method for manufacturing semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US06943125B2
公开(公告)日：2005-09-13
申请号：US10739248
申请日：2003-12-18
申请人： Ga Won Lee , Jae Hoon Choi , Jae Chul Om , Sung Wook Park , Jae Hee Lee
发明人： Ga Won Lee , Jae Hoon Choi , Jae Chul Om , Sung Wook Park , Jae Hee Lee
IPC分类号： H01L21/31 , H01L21/265 , H01L21/336 , H01L21/44 , H01L21/469 , H01L21/768 , H01L29/16 , H01L29/78
CPC分类号： H01L29/6656 , H01L21/265 , H01L21/76825 , H01L21/76828 , H01L21/76834 , H01L29/78 , Y10S438/958
摘要： Provided is a method for manufacturing a semiconductor device including a plurality of different semiconductor elements with a transistor for fabricating the semiconductor device formed on a semiconductor substrate, an interlayer insulation film formed all over the upper part, and a hole trap site formed in the interlayer insulation film for preventing a mobile ion like H or moisture from penetrating, whereby it can be prevented that a leakage current increases abnormally where the voltage difference (Vgs) is lower than a threshold voltage.
摘要翻译：提供一种半导体器件的制造方法，该半导体器件包括多个不同的半导体元件，其具有用于制造形成在半导体衬底上的半导体器件的晶体管，在上部形成的层间绝缘膜，以及形成在中间层中的空穴陷阱部位用于防止像H或湿气这样的移动离子渗透的绝缘膜，从而可以防止当电压差（Vgs）低于阈值电压时漏电流异常增加。

2. 发明授权

US07727839B2 Method of manufacturing NAND flash memory device 失效
标题翻译：制造NAND闪存器件的方法
公开(公告)号：US07727839B2
公开(公告)日：2010-06-01
申请号：US11646956
申请日：2006-12-28
申请人： Jae Chul Om , Nam Kyeong Kim
发明人： Jae Chul Om , Nam Kyeong Kim
IPC分类号： H01L21/8239
CPC分类号： H01L27/115 , H01L27/11521 , H01L29/66621
摘要： A method of manufacturing a NAND flash memory device is disclosed. A semiconductor substrate of a portion in which a source select line SSL and a drain select line DSL will be formed is recessed selectively or entirely to a predetermined depth. Accordingly, the channel length of a gate can be increased and disturbance can be reduced. It is therefore possible to improve the reliability and yield of devices.
摘要翻译：公开了制造NAND闪速存储器件的方法。其中将形成源极选择线SSL和漏极选择线DSL的部分的半导体衬底被选择性地或完全地凹入到预定深度。因此，可以增加栅极的沟道长度并减小干扰。因此可以提高装置的可靠性和产量。

3. 发明授权

US08044454B2 Non-volatile memory device 失效
标题翻译：非易失性存储器件
公开(公告)号：US08044454B2
公开(公告)日：2011-10-25
申请号：US12489785
申请日：2009-06-23
申请人： Jae Chul Om
发明人： Jae Chul Om
IPC分类号： H01L29/66
CPC分类号： H01L27/11568 , H01L21/28114 , H01L27/115 , H01L27/11524 , H01L29/42376
摘要： A non-volatile memory device having a SONOS structure and a manufacturing method thereof, where a conductive layer is formed between a charge trap layer and a blocking insulation layer of the SONOS structure. Therefore, when a voltage is applied to a gate, the conductive layer undergoes voltage distributions. Accordingly, a desired voltage can be applied to the blocking insulation layer, the charge trap layer and the tunnel insulating layer by controlling the effective oxide thickness (EOT) of the blocking insulation layer and the EOT of the charge trap layer and the tunnel insulating layer. It is therefore possible to improve the erase speed of a cell.
摘要翻译：具有SONOS结构的非易失性存储器件及其制造方法，其中在电荷陷阱层和SONOS结构的阻挡绝缘层之间形成导电层。因此，当向栅极施加电压时，导电层经受电压分布。因此，通过控制阻挡绝缘层的有效氧化物厚度（EOT）和电荷陷阱层和隧道绝缘层的EOT，可以对阻挡绝缘层，电荷陷阱层和隧道绝缘层施加期望的电压。因此，可以提高电池的擦除速度。

4. 发明申请

US20080153227A1 NAND FLASH MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译： NAND闪存存储器件及其制造方法
公开(公告)号：US20080153227A1
公开(公告)日：2008-06-26
申请号：US12041949
申请日：2008-03-04
申请人： Jae Chul Om , Nam Kyeong Kim , Se Jun Kim
发明人： Jae Chul Om , Nam Kyeong Kim , Se Jun Kim
IPC分类号： H01L21/336
CPC分类号： H01L29/7881 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L29/66825
摘要： A NAND flash memory device and method of manufacturing the same is disclosed. Source and drain select transistor gates are recessed lower than an active region of a semiconductor substrate. A valid channel length of the source and drain select transistor gates is longer than a channel length of memory cell gates. Accordingly, an electric field between a source region and a drain region of the select transistor can be reduced. It is thus possible to prevent program disturbance from occurring in edge memory cells adjacent to the source and drain select transistors in non-selected cell strings.
摘要翻译：公开了NAND闪速存储器件及其制造方法。源极和漏极选择晶体管栅极比半导体衬底的有源区域低。源极和漏极选择晶体管栅极的有效沟道长度比存储器单元栅极的沟道长度长。因此，可以减小选择晶体管的源极区域和漏极区域之间的电场。因此，可以防止在非选择的单元串中与源极和漏极选择晶体管相邻的边缘存储单元中发生程序干扰。

5. 发明申请

US20070155098A1 Method of manufacturing NAND flash memory device 失效
标题翻译：制造NAND闪存器件的方法
公开(公告)号：US20070155098A1
公开(公告)日：2007-07-05
申请号：US11646956
申请日：2006-12-28
申请人： Jae Chul Om , Nam Kyeong Kim
发明人： Jae Chul Om , Nam Kyeong Kim
IPC分类号： H01L21/336 , H01L29/788 , H01L29/78
CPC分类号： H01L27/115 , H01L27/11521 , H01L29/66621
摘要： A method of manufacturing a NAND flash memory device is disclosed. A semiconductor substrate of a portion in which a source select line SSL and a drain select line DSL will be formed is recessed selectively or entirely to a predetermined depth. Accordingly, the channel length of a gate can be increased and disturbance can be reduced. It is therefore possible to improve the reliability and yield of devices.
摘要翻译：公开了制造NAND闪速存储器件的方法。其中将形成源极选择线SSL和漏极选择线DSL的部分的半导体衬底被选择性地或完全地凹入到预定深度。因此，可以增加栅极的沟道长度并减小干扰。因此可以提高装置的可靠性和产量。

6. 发明授权

US08106448B2 NAND flash memory device 失效
标题翻译： NAND闪存设备
公开(公告)号：US08106448B2
公开(公告)日：2012-01-31
申请号：US12762778
申请日：2010-04-19
申请人： Jae Chul Om , Nam Kyeong Kim
发明人： Jae Chul Om , Nam Kyeong Kim
IPC分类号： H01L29/772
CPC分类号： H01L27/115 , H01L27/11521 , H01L29/66621
摘要： A method of manufacturing a NAND flash memory device. A semiconductor substrate of a portion in which a source select line SSL and a drain select line DSL will be formed is recessed selectively or entirely to a predetermined depth. Accordingly, the channel length of a gate can be increased and disturbance can be reduced. It is therefore possible to improve the reliability and yield of devices.
摘要翻译：一种制造NAND闪速存储器件的方法。其中将形成源极选择线SSL和漏极选择线DSL的部分的半导体衬底被选择性地或完全地凹入到预定深度。因此，可以增加栅极的沟道长度并减小干扰。因此可以提高装置的可靠性和产量。

7. 发明申请

US20090269895A1 Method of Manufacturing Non-Volatile Memory Device 有权
标题翻译：制造非易失性存储器件的方法
公开(公告)号：US20090269895A1
公开(公告)日：2009-10-29
申请号：US12497280
申请日：2009-07-02
申请人： Nam Kyeong Kim , Jae Chul Om
发明人： Nam Kyeong Kim , Jae Chul Om
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , H01L27/11568
摘要： Non-volatile memory devices and a method of manufacturing the same, wherein data storage of two bits per cell is enabled and the devices can pass the limit in terms of layout, whereby channel length can be controlled. The non-volatile memory device includes gate lines formed in one direction on a semiconductor substrate in which trenches are formed, wherein the gate lines gap-fill the trenches, a dielectric layer formed between the semiconductor substrate and the gate lines, bit separation insulating layers formed between the semiconductor substrate and the dielectric layer under the trenches, and isolation structures formed by etching the trenches, and the dielectric layer and the semiconductor substrate between the trenches in a line form vertical to the gate lines and gap-filling an insulating layer.
摘要翻译：非易失性存储器件及其制造方法，其中每个单元的两位的数据存储被使能，并且器件可以通过布局方面的限制，从而可以控制通道长度。非易失性存储器件包括在其中形成有沟槽的半导体衬底上沿一个方向形成的栅极线，其中栅极间隙填充沟槽，形成在半导体衬底和栅极线之间的电介质层，位分离绝缘层形成在沟槽下方的半导体衬底和电介质层之间，并且通过蚀刻沟槽形成的隔离结构，并且沟槽之间的电介质层和沟槽之间的半导体衬底垂直于栅极线并间隙填充绝缘层。

8. 发明申请

US20090261404A1 Non-volatile Memory Device 失效
标题翻译：非易失性存储器件
公开(公告)号：US20090261404A1
公开(公告)日：2009-10-22
申请号：US12489785
申请日：2009-06-23
申请人： Jae Chul Om
发明人： Jae Chul Om
IPC分类号： H01L29/792
CPC分类号： H01L27/11568 , H01L21/28114 , H01L27/115 , H01L27/11524 , H01L29/42376
摘要： A non-volatile memory device having a SONOS structure and a manufacturing method thereof, where a conductive layer is formed between a charge trap layer and a blocking insulation layer of the SONOS structure. Therefore, when a voltage is applied to a gate, the conductive layer undergoes voltage distributions. Accordingly, a desired voltage can be applied to the blocking insulation layer, the charge trap layer and the tunnel insulating layer by controlling the effective oxide thickness (EOT) of the blocking insulation layer and the EOT of the charge trap layer and the tunnel insulating layer. It is therefore possible to improve the erase speed of a cell.
摘要翻译：具有SONOS结构的非易失性存储器件及其制造方法，其中在电荷陷阱层和SONOS结构的阻挡绝缘层之间形成导电层。因此，当向栅极施加电压时，导电层经受电压分布。因此，通过控制阻挡绝缘层的有效氧化物厚度（EOT）和电荷陷阱层和隧道绝缘层的EOT，可以对阻挡绝缘层，电荷陷阱层和隧道绝缘层施加期望的电压。因此，可以提高电池的擦除速度。

9. 发明授权

US07573089B2 Non-volatile memory device 失效
标题翻译：非易失性存储器件
公开(公告)号：US07573089B2
公开(公告)日：2009-08-11
申请号：US11634570
申请日：2006-12-06
申请人： Nam Kyeong Kim , Jae Chul Om
发明人： Nam Kyeong Kim , Jae Chul Om
IPC分类号： H01L29/76
CPC分类号： H01L27/115 , H01L27/11568
摘要： Non-volatile memory devices and a method of manufacturing the same, wherein data storage of two bits per cell is enabled and the devices can pass the limit in terms of layout, whereby channel length can be controlled. The non-volatile memory device includes gate lines formed in one direction on a semiconductor substrate in which trenches are formed, wherein the gate lines gap-fill the trenches, a dielectric layer formed between the semiconductor substrate and the gate lines, bit separation insulating layers formed between the semiconductor substrate and the dielectric layer under the trenches, and isolation structures formed by etching the trenches, and the dielectric layer and the semiconductor substrate between the trenches in a line form vertical to the gate lines and gap-filling an insulating layer.
摘要翻译：非易失性存储器件及其制造方法，其中每个单元的两位的数据存储被使能，并且器件可以通过布局方面的限制，从而可以控制通道长度。非易失性存储器件包括在其中形成有沟槽的半导体衬底上沿一个方向形成的栅极线，其中栅极间隙填充沟槽，形成在半导体衬底和栅极线之间的电介质层，位分离绝缘层形成在沟槽下方的半导体衬底和电介质层之间，并且通过蚀刻沟槽形成的隔离结构，并且沟槽之间的电介质层和沟槽之间的半导体衬底垂直于栅极线并间隙填充绝缘层。

10. 发明授权

US07456466B2 NAND flash memory device and method of manufacturing the same 有权
标题翻译： NAND闪存器件及其制造方法
公开(公告)号：US07456466B2
公开(公告)日：2008-11-25
申请号：US11445770
申请日：2006-06-02
申请人： Jae Chul Om , Nam Kyeong Kim , Se Jun Kim
发明人： Jae Chul Om , Nam Kyeong Kim , Se Jun Kim
IPC分类号： H01L21/336 , H01L29/76
CPC分类号： H01L29/7881 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L29/66825
摘要： A NAND flash memory device and method of manufacturing the same is disclosed. Source and drain select transistor gates are recessed lower than an active region of a semiconductor substrate. A valid channel length of the source and drain select transistor gates is longer than a channel length of memory cell gates. Accordingly, an electric field between a source region and a drain region of the select transistor can be reduced. It is thus possible to prevent program disturbance from occurring in edge memory cells adjacent to the source and drain select transistors in non-selected cell strings.
摘要翻译：公开了NAND闪速存储器件及其制造方法。源极和漏极选择晶体管栅极比半导体衬底的有源区域低。源极和漏极选择晶体管栅极的有效沟道长度比存储器单元栅极的沟道长度长。因此，可以减小选择晶体管的源极区域和漏极区域之间的电场。因此，可以防止在非选择的单元串中与源极和漏极选择晶体管相邻的边缘存储单元中发生程序干扰。

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