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1. 发明申请

US20070115046A1 METHOD AND APPARATUS FOR TUNING GMC FILTER 有权
标题翻译：用于调整GMC过滤器的方法和装置
公开(公告)号：US20070115046A1
公开(公告)日：2007-05-24
申请号：US11623686
申请日：2007-01-16
申请人： GOLAM CHOWDHURY , DOUGLAS HOLBERG
发明人： GOLAM CHOWDHURY , DOUGLAS HOLBERG
IPC分类号： H03B1/00
CPC分类号： H03H11/04 , H03B5/14 , H03F1/342 , H03F3/45183 , H03F2203/45318 , H03F2203/45366 , H03L7/0995
摘要： A system and method for providing a tunable GMC filter is disclosed wherein a transconducted element having an attenuator in a feedback loop therewith is allowed to oscillate at a first oscillation frequency. An input to the filter enables tuning of the oscillation frequency to a pre-determined frequency.
摘要翻译：公开了一种用于提供可调GMC滤波器的系统和方法，其中具有与其反馈回路中的衰减器的跨导元件被允许以第一振荡频率振荡。滤波器的输入使振荡频率调谐到预定频率。

2. 发明申请

US20070216548A1 INTEGRATED CIRCUIT PACKAGE INCLUDING PROGRAMMABLE OSCILLATORS 有权
标题翻译：集成电路封装，包括可编程振荡器
公开(公告)号：US20070216548A1
公开(公告)日：2007-09-20
申请号：US11694624
申请日：2007-03-30
申请人： DONALD ALFANO , DANNY ALLRED , DOUGLAS PIASECKI , KENNETH FERNALD , KA LEUNG , BRIAN CALOWAY , ALVIN STORVIK , PAUL HIGHLEY , DOUGLAS HOLBERG
发明人： DONALD ALFANO , DANNY ALLRED , DOUGLAS PIASECKI , KENNETH FERNALD , KA LEUNG , BRIAN CALOWAY , ALVIN STORVIK , PAUL HIGHLEY , DOUGLAS HOLBERG
IPC分类号： H03M7/00
CPC分类号： G06F13/385 , G06F1/08 , G06F15/7814 , H03M1/122 , H03M1/183 , H03M1/462 , Y02D10/12 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： An integrated circuit package includes a processing core and an internal oscillator. The processing core operates on a set of instructions to carry out predefined processes. The internal oscillator provides a system clock for the integrated circuit package. The internal oscillator has associated therewith an internal control register for controlling the operation of the internal oscillator responsive to control bits of the internal oscillator controlled by the processing core.
摘要翻译：集成电路封装包括处理核心和内部振荡器。处理核心通过一组指令来执行预定义的过程。内部振荡器为集成电路封装提供系统时钟。内部振荡器具有与其相关联的内部控制寄存器，用于响应于由处理核心控制的内部振荡器的控制位来控制内部振荡器的操作。

3. 发明申请

US20070103357A1 ANALOG-TO-DIGITAL CONVERTER WITH LOW POWER TRACK-AND-HOLD MODE 有权
标题翻译：具有低功率跟踪和保持模式的模拟数字转换器
公开(公告)号：US20070103357A1
公开(公告)日：2007-05-10
申请号：US11618644
申请日：2006-12-29
申请人： DONALD ALFANO , DANNY ALLRED , DOUGLAS PIASECKI , KENNETH FERNALD , KA LEUNG , BRIAN CALOWAY , ALVIN STORVIK , PAUL HIGHLEY , DOUGLAS HOLBERG
发明人： DONALD ALFANO , DANNY ALLRED , DOUGLAS PIASECKI , KENNETH FERNALD , KA LEUNG , BRIAN CALOWAY , ALVIN STORVIK , PAUL HIGHLEY , DOUGLAS HOLBERG
IPC分类号： H03M1/12
CPC分类号： G06F13/385 , G06F1/08 , G06F15/7814 , H03M1/122 , H03M1/183 , H03M1/462 , Y02D10/12 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： A method for converting analog data to digital data is disclosed. The method includes operating an analog-to-digital data converter in a tracking mode to sample an input signal and in a convert mode to convert the sampled input signal after sampling to a digital signal. The analog-to-digital data converter is controlled with a controller to operate in different modes of operation by providing at least one step wherein the tracking mode of operation is controlled to initiate at a predetermined time to begin the sampling operation.
摘要翻译：公开了一种将模拟数据转换为数字数据的方法。该方法包括以跟踪模式操作模拟数字数据转换器，以对输入信号进行采样，并以转换模式对采样后的采样输入信号进行数字信号转换。模拟数字数据转换器由控制器控制，以通过提供至少一个步骤操作在不同的操作模式，其中跟踪操作模式被控制以在预定时间开始以开始采样操作。

4. 发明申请

US20070300047A1 RECONFIGURABLE PROCESSOR INTEGRATED CIRCUIT 有权
标题翻译：可重构处理器集成电路
公开(公告)号：US20070300047A1
公开(公告)日：2007-12-27
申请号：US11772184
申请日：2007-06-30
申请人： DONALD ALFANO , DANNY ALLRED , DOUGLAS PIASECKI , KENNETH FERNALD , KA LEUNG , BRIAN CALOWAY , ALVIN STORVIK , PAUL HIGHLEY , DOUGLAS HOLBERG
发明人： DONALD ALFANO , DANNY ALLRED , DOUGLAS PIASECKI , KENNETH FERNALD , KA LEUNG , BRIAN CALOWAY , ALVIN STORVIK , PAUL HIGHLEY , DOUGLAS HOLBERG
IPC分类号： G06F13/00
CPC分类号： G06F13/385 , G06F1/08 , G06F15/7814 , H03M1/122 , H03M1/183 , H03M1/462 , Y02D10/12 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： A reconfigurable processor includes a processor core for operating on a set of instructions to carry out predefined processes and includes a plurality of input/output pins in addition to a plurality of functional input/output blocks. These functional blocks allow the processing core to interface with the plurality of input/output pins, each of the functional input/output blocks having an associated and predetermined functionality. This functionality comprises the output as a function of the input, the function defined by the functionality. Each of the functional input/output blocks has a requirement for a defined number of the plurality of input/output pins wherein the total of the defined number for all of the plurality of functional input/output blocks exceeds the number of the plurality of input/output pins and wherein the processor core is interfaced with one of the input or output of each of the functional blocks. A reconfigurable interface selectively interfaces between the other of the input or output of the functional blocks and a select one or ones of the plurality of input/output pins, such that the processor core can be interfaced with the select one or ones of the input/output pins. The reconfigurable interface is operable to define how each of the plurality of input/output pins interfaces with the select ones of the plurality of functional blocks and the associated functionality in accordance with configuration information. A non-volatile memory is provided for storing information for use in association with the configuration information, such that the stored information can be altered.
摘要翻译：可重构处理器包括用于在一组指令上操作以执行预定义的处理的处理器核心，并且除了多个功能输入/输出块之外还包括多个输入/输出引脚。这些功能块允许处理核与多个输入/输出引脚相连接，每个功能输入/输出块具有相关联的和预定的功能。该功能包括作为输入的功能的输出，功能定义的功能。每个功能输入/输出块对多个输入/输出引脚的定义数量要求，其中所有多个功能输入/输出块中的所有定义数目的总数超过多个输入/ 输出引脚，并且其中处理器核心与每个功能块的输入或输出中的一个接口。可重配置接口选择性地在功能块的输入或输出中的另一个与多个输入/输出引脚中的选择一个或多个输入/输出引脚之间进行接口，使得处理器核可以与选择的一个或多个输入/ 输出引脚。可重配置接口可操作以根据配置信息定义多个输入/输出引脚中的每一个如何与多个功能块中的选择功能块和相关联的功能接口。提供非易失性存储器用于存储与配置信息相关联使用的信息，使得可以改变所存储的信息。

5. 发明申请

US20070296478A1 INTEGRATED CIRCUIT PACKAGE INCLUDING PROGRAMMABLE COMPARATORS 有权
标题翻译：集成电路封装，包括可编程比较器
公开(公告)号：US20070296478A1
公开(公告)日：2007-12-27
申请号：US11694629
申请日：2007-03-30
申请人： DONALD ALFANO , DANNY ALLRED , DOUGLAS PIASECKI , KENNETH FERNALD , KA LEUNG , BRIAN CALOWAY , ALVIN STORVIK , PAUL HIGHLEY , DOUGLAS HOLBERG
发明人： DONALD ALFANO , DANNY ALLRED , DOUGLAS PIASECKI , KENNETH FERNALD , KA LEUNG , BRIAN CALOWAY , ALVIN STORVIK , PAUL HIGHLEY , DOUGLAS HOLBERG
IPC分类号： H03H11/26
CPC分类号： G06F13/385 , G06F1/08 , G06F15/7814 , H03M1/122 , H03M1/183 , H03M1/462 , Y02D10/12 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： An integrated circuit package includes a processing core for operating on a set of instructions to carry out predefined processes. A plurality of comparators perform compare operations within the integrated circuit package. At least one control register is associated with each of the plurality of comparators. The plurality of comparators are programmable to operate in a plurality of operating modes responsive to control bits established in the at least one control register by the processing core.
摘要翻译：集成电路封装包括用于对一组指令进行操作以执行预定义的处理的处理核心。多个比较器执行集成电路封装内的比较操作。至少一个控制寄存器与多个比较器中的每一个相关联。多个比较器可编程为响应于由处理核心在至少一个控制寄存器中建立的控制位而以多种操作模式操作。

6. 发明申请

US20090187773A1 MCU WITH POWER SAVING MODE 有权
标题翻译：具有省电模式的MCU
公开(公告)号：US20090187773A1
公开(公告)日：2009-07-23
申请号：US12255127
申请日：2008-10-21
申请人： DOUGLAS F. PASTORELLO , DOUGLAS HOLBERG , WILLIAM GENE DURBIN , BIRANCHINATH SAHU , GOLAM R. CHOWDHURY
发明人： DOUGLAS F. PASTORELLO , DOUGLAS HOLBERG , WILLIAM GENE DURBIN , BIRANCHINATH SAHU , GOLAM R. CHOWDHURY
IPC分类号： G06F1/26 , G05F1/00 , G06F1/00
CPC分类号： G06F1/3203 , H03K19/0016
摘要： A microcontroller unit includes a processor for generating a first control signal to start a comatose mode of operation for the microcontroller unit. Control logic responsive to the first control signal generates an enable signal at a first level and the control logic is further responsive to a second control signal for generating the enable signal at a second level. A voltage regulator generates regulated voltage from an input voltage. The voltage regulator shuts down to provide a zero volt regulated voltage responsive to the enable signal at the first level and powers up to provide a regulated voltage at an operating level responsive to the enable signal at the second level.
摘要翻译：微控制器单元包括用于产生第一控制信号以开始微控制器单元的昏迷模式的处理器。响应于第一控制信号的控制逻辑在第一电平产生使能信号，并且控制逻辑还响应于第二控制信号，以在第二电平产生使能信号。电压调节器从输入电压产生调节电压。电压调节器关闭，以响应于在第一电平的使能信号提供零伏调节电压，并且上电以响应于在第二电平的使能信号提供处于工作电平的调节电压。

7. 发明申请

US20070300046A1 SYSTEM AND METHOD FOR PROGRAMMING INTEGRATED CIRCUIT PACKAGE VIA JTAG INTERFACE 审中-公开
标题翻译：用于通过JTAG接口编程集成电路封装的系统和方法
公开(公告)号：US20070300046A1
公开(公告)日：2007-12-27
申请号：US11694610
申请日：2007-03-30
申请人： DONALD ALFANO , DANNY ALLRED , DOUGLAS PIASECKI , KENNETH FERNALD , KA LEUNG , BRIAN CALOWAY , ALVIN STORVIK , PAUL HIGHLEY , DOUGLAS HOLBERG
发明人： DONALD ALFANO , DANNY ALLRED , DOUGLAS PIASECKI , KENNETH FERNALD , KA LEUNG , BRIAN CALOWAY , ALVIN STORVIK , PAUL HIGHLEY , DOUGLAS HOLBERG
IPC分类号： G06F9/44
CPC分类号： G06F13/385 , G06F1/08 , G06F15/7814 , H03M1/122 , H03M1/183 , H03M1/462 , Y02D10/12 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： An integrated circuit package includes a processing core for operating on a set of instructions to carry out predefined processes. A flash memory stores instructions within the integrated circuit package. A plurality of registers stores data and the program instructions during execution of the program instructions. A JTAG interface provides an interface with the integrated circuit package and enables interactions with the processing core and the plurality of registers. Emulation logic enables manipulating and monitoring program flow through the JTAG interface during execution of the program instructions.
摘要翻译：集成电路封装包括用于对一组指令进行操作以执行预定义的处理的处理核心。闪存存储集成电路封装内的指令。多个寄存器在执行程序指令期间存储数据和程序指令。 JTAG接口提供与集成电路封装的接口，并实现与处理核心和多个寄存器的交互。仿真逻辑可以在程序指令执行过程中通过JTAG接口操作和监视程序流程。

8. 发明申请

US20070233912A1 PRECISION OSCILLATOR HAVING LINBUS CAPABILITIES 失效
标题翻译：具有LINBUS能力的精密振荡器
公开(公告)号：US20070233912A1
公开(公告)日：2007-10-04
申请号：US11618581
申请日：2006-12-29
申请人： DOUGLAS PIASECKI , DOUGLAS HOLBERG
发明人： DOUGLAS PIASECKI , DOUGLAS HOLBERG
IPC分类号： G06F3/00
CPC分类号： H03K3/0231 , H03K3/356113 , H03K5/2481
摘要： The integrated system on a chip with LINBUS network communication capabilities includes processing circuitry for performing predefined digital processing functionalities on the chip. A free running clock circuit generates a temperature compensated clock that does not require a synch signal from external to the chip. A LINBUS network communications interface digitally communicates with off-chip LINBUS devices. Communication between said on-chip LINBUS communications interface and the off-chip LINBUS devices is affected without clock recovery. The LINBUS network communication interface has a time base derived from the temperature compensated clock which is independent of any timing information in the input data received during a receive operation. The temperature compensated clock further provides an on-chip time reference for both the processing circuitry and the LINBUS network communications interface.
摘要翻译：具有LINBUS网络通信能力的芯片上的集成系统包括用于在芯片上执行预定义的数字处理功能的处理电路。自由运行的时钟电路产生温度补偿时钟，不需要来自芯片外部的同步信号。 LINBUS网络通信接口与片外LINBUS设备进行数字通信。所述片上LINBUS通信接口和片外LINBUS器件之间的通信不受时钟恢复的影响。 LINBUS网络通信接口具有从温度补偿时钟导出的时基，其独立于在接收操作期间接收的输入数据中的任何定时信息。温度补偿时钟还为处理电路和LINBUS网络通信接口提供片上时间参考。

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