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1. 发明授权

US10483461B2 Embedded MRAM in interconnects and method for producing the same 有权
公开(公告)号：US10483461B2
公开(公告)日：2019-11-19
申请号：US15957506
申请日：2018-04-19
申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.
发明人： Wanbing Yi , Curtis Chun-I Hsieh , Yi Jiang , Bharat Bhushan , Mahesh Bhatkar , Juan Boon Tan
IPC分类号： H01L27/22 , H01L43/12 , H01L23/522 , H01L43/02 , H01L43/08
摘要： Method of forming embedded MRAM in interconnects using a metal hard mask process and the resulting device are provided. Embodiments include forming a first interlayer dielectric (ILD) layer including a first metal (Mx) level; forming a capping layer over the first ILD layer; forming magnetic tunnel junction (MTJ) structures formed in a second ILD over the first capping layer; forming a second metal (Mx+1) level in the second ILD layer; forming a second capping layer over the second ILD layer; and forming a third metal (Mx+2) level in a third ILD layer over the second capping layer.

2. 发明授权

US09773702B2 Device without zero mark layer 有权
公开(公告)号：US09773702B2
公开(公告)日：2017-09-26
申请号：US14981873
申请日：2015-12-28
申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.
发明人： Shunqiang Gong , Juan Boon Tan , Shijie Wang , Mahesh Bhatkar , Daxiang Wang
IPC分类号： H01L21/4763 , H01L21/768 , H01L23/544 , H01L23/525
CPC分类号： H01L21/76898 , H01L23/525 , H01L23/544 , H01L2223/5442 , H01L2223/54426 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： Devices and methods for forming a device are disclosed. The method includes providing a substrate having first and second surfaces. At least one through silicon via (TSV) opening is formed in the substrate. The TSV opening extends through the first and second surfaces of the substrate. An alignment trench corresponding to an alignment mark is formed in the substrate. The alignment trench extends from the first surface of the substrate to a depth shallower than a depth of the TSV opening. A dielectric liner layer is provided over the substrate. The dielectric liner layer at least lines sidewalls of the TSV opening. A conductive layer is provided over the substrate. The conductive layer fills at least the TSV opening to form TSV contact. A redistribution layer (RDL) is formed over the substrate. The RDL layer is patterned using a reticle to form at least one opening which corresponds to a TSV contact pad. The reticle is aligned using the alignment mark in the substrate.

3. 发明授权

US10566384B2 Two pass MRAM dummy solution 有权
公开(公告)号：US10566384B2
公开(公告)日：2020-02-18
申请号：US16175216
申请日：2018-10-30
申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.
发明人： Wanbing Yi , Neha Nayyar , Curtis Chun-I Hsieh , Mahesh Bhatkar , Wenjun Liu , Juan Boon Tan
IPC分类号： H01L27/22
摘要： Methods of fabricating a flexible dummy fill to increase MTJ density are provided. Embodiments include forming a first oxide layer; forming lower interconnect layers in the first oxide layer; forming a nitride layer over the first oxide layer and the lower interconnect layers; forming a second oxide layer over the nitride layer; forming bottom electrodes through the second oxide layer and the nitride layer contacting a portion of an upper surface of the lower interconnect layers; forming MTJ structures over the bottom electrodes; forming top electrodes over the MTJ structures; and forming upper interconnect layers over one or more of the top electrodes.

4. 发明授权

US10158066B1 Two pass MRAM dummy solution 有权
公开(公告)号：US10158066B1
公开(公告)日：2018-12-18
申请号：US15616624
申请日：2017-06-07
申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.
发明人： Wanbing Yi , Neha Nayyar , Curtis Chun-I Hsieh , Mahesh Bhatkar , Wenjun Liu , Juan Boon Tan
IPC分类号： H01L21/00 , H01L43/12 , H01L43/02 , H01L43/08
摘要： Methods of fabricating a flexible dummy fill to increase MTJ density are provided. Embodiments include forming a first oxide layer; forming lower interconnect layers in the first oxide layer; forming a nitride layer over the first oxide layer and the lower interconnect layers; forming a second oxide layer over the nitride layer; forming bottom electrodes through the second oxide layer and the nitride layer contacting a portion of an upper surface of the lower interconnect layers; forming MTJ structures over the bottom electrodes; forming top electrodes over the MTJ structures; and forming upper interconnect layers over one or more of the top electrodes.

5. 发明申请

US20180342556A1 INTEGRATED CIRCUITS WITH VERTICAL CAPACITORS AND METHODS FOR PRODUCING THE SAME 审中-公开
公开(公告)号：US20180342556A1
公开(公告)日：2018-11-29
申请号：US15992811
申请日：2018-05-30
申请人： Globalfoundries Singapore Pte. Ltd.
发明人： Juan Boon Tan , Mahesh Bhatkar , Bhushan Bharat , Wanbing Yi
IPC分类号： H01L27/22 , H01L43/02 , H01L23/522
CPC分类号： H01L27/222 , H01L23/5223 , H01L28/60 , H01L28/91 , H01L43/02 , H01L43/08 , H01L43/12
摘要： Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, an integrated circuit includes a capacitor, where the capacitor includes a first capacitor plate and a second capacitor plate. The first capacitor plate includes a first memory cell, and the second capacitor plate includes a second memory cell. The capacitor is utilized as a functional capacitor in the integrated circuit.

6. 发明申请

US20160190041A1 DEVICE WITHOUT ZERO MARK LAYER 有权
标题翻译：没有零标记层的设备
公开(公告)号：US20160190041A1
公开(公告)日：2016-06-30
申请号：US14981873
申请日：2015-12-28
申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.
发明人： Shunqiang Gong , Juan Boon Tan , Shijie Wang , Mahesh Bhatkar , Daxiang Wang
IPC分类号： H01L23/48 , H01L21/768 , H01L23/544 , H01L23/528
CPC分类号： H01L21/76898 , H01L23/525 , H01L23/544 , H01L2223/5442 , H01L2223/54426 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： Devices and methods for forming a device are disclosed. The method includes providing a substrate having first and second surfaces. At least one through silicon via (TSV) opening is formed in the substrate. The TSV opening extends through the first and second surfaces of the substrate. An alignment trench corresponding to an alignment mark is formed in the substrate. The alignment trench extends from the first surface of the substrate to a depth shallower than a depth of the TSV opening. A dielectric liner layer is provided over the substrate. The dielectric liner layer at least lines sidewalls of the TSV opening. A conductive layer is provided over the substrate. The conductive layer fills at least the TSV opening to form TSV contact. A redistribution layer (RDL) is formed over the substrate. The RDL layer is patterned using a reticle to form at least one opening which corresponds to a TSV contact pad. The reticle is aligned using the alignment mark in the substrate.
摘要翻译：公开了用于形成装置的装置和方法。该方法包括提供具有第一表面和第二表面的基底。在衬底中形成至少一个通硅通孔（TSV）开口。 TSV开口延伸穿过衬底的第一和第二表面。在基板上形成与对准标记对应的对准沟槽。对准沟槽从衬底的第一表面延伸到比TSV开口的深度浅的深度。介电衬里层设置在衬底上。电介质衬垫层至少对TSV开口的侧壁进行排列。导电层设置在衬底上。导电层填充至少TSV开口以形成TSV接触。在衬底上形成再分布层（RDL）。使用掩模版图案化RDL层以形成对应于TSV接触焊盘的至少一个开口。使用衬底中的对准标记对准标线。

7. 发明授权

US09917027B2 Integrated circuits with aluminum via structures and methods for fabricating the same 有权
公开(公告)号：US09917027B2
公开(公告)日：2018-03-13
申请号：US14985256
申请日：2015-12-30
申请人： Globalfoundries Singapore Pte. Ltd.
发明人： Wanbing Yi , Mahesh Bhatkar , Chin Chuan Neo , Juan Boon Tan
IPC分类号： H01L21/28 , H01L21/311 , H01L21/768 , H01L23/528 , H01L23/31 , H01L23/532 , H01L21/56 , H01L23/29
CPC分类号： H01L23/3192 , H01L21/56 , H01L21/76804 , H01L21/76816 , H01L21/76877 , H01L23/291 , H01L23/528 , H01L23/53214 , H01L23/53228
摘要： A method for fabricating an integrated circuit includes forming a first opening in an upper dielectric layer, the first opening having a first width, forming a second opening in a lower dielectric layer, the lower dielectric layer being below the upper dielectric layer, the second opening having a second width that is narrower than the first width, the second opening being substantially centered underneath the first opening so as to form a stepped via structure, conformally depositing an aluminum material layer in the stepped via structure and over the upper dielectric layer, and forming a passivation layer over the aluminum material layer.

8. 发明授权

US09728474B1 Semiconductor chips with seal rings and electronic test structures, semiconductor wafers including the semiconductor chips, and methods for fabricating the same 有权
公开(公告)号：US09728474B1
公开(公告)日：2017-08-08
申请号：US15278257
申请日：2016-09-28
申请人： Globalfoundries Singapore Pte. Ltd.
发明人： Wanbing Yi , Juan Boon Tan , Mahesh Bhatkar , Danny Pak-Chum Shum
IPC分类号： H01L23/10 , H01L21/66 , H01L23/31 , H01L23/485 , H01L43/08
CPC分类号： H01L22/32 , H01L22/34 , H01L23/10 , H01L23/3171 , H01L23/485 , H01L23/585 , H01L27/222 , H01L43/08
摘要： A semiconductor chip includes an active area including a plurality of integrated circuit structures, a seal ring enclosing the active area, a corner area of the semiconductor chip that is outside of the seal ring, and an electronic test structure disposed within the corner area. Semiconductor wafers including the above-noted semiconductor chips, as well as methods for fabricating semiconductor wafers including the above-noted semiconductor chips, are also disclosed.

9. 发明申请

US20170194229A1 INTEGRATED CIRCUITS WITH ALUMINUM VIA STRUCTURES AND METHODS FOR FABRICATING THE SAME 有权
公开(公告)号：US20170194229A1
公开(公告)日：2017-07-06
申请号：US14985256
申请日：2015-12-30
申请人： Globalfoundries Singapore Pte. Ltd.
发明人： Wanbing Yi , Mahesh Bhatkar , Chin Chuan Neo , Juan Boon Tan
IPC分类号： H01L23/31 , H01L23/29 , H01L23/532 , H01L21/56 , H01L21/768 , H01L23/528
CPC分类号： H01L23/3192 , H01L21/56 , H01L21/76804 , H01L21/76816 , H01L21/76877 , H01L23/291 , H01L23/528 , H01L23/53214 , H01L23/53228
摘要： A method for fabricating an integrated circuit includes forming a first opening in an upper dielectric layer, the first opening having a first width, forming a second opening in a lower dielectric layer, the lower dielectric layer being below the upper dielectric layer, the second opening having a second width that is narrower than the first width, the second opening being substantially centered underneath the first opening so as to form a stepped via structure, conformally depositing an aluminum material layer in the stepped via structure and over the upper dielectric layer, and forming a passivation layer over the aluminum material layer.

10. 发明授权

US09613897B2 Integrated circuits including magnetic core inductors and methods for fabricating the same 有权
公开(公告)号：US09613897B2
公开(公告)日：2017-04-04
申请号：US14537942
申请日：2014-11-11
申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.
发明人： Mahesh Bhatkar , Lulu Peng , Wanbing Yi , Juan Boon Tan , Luke England
IPC分类号： H01F5/00 , H01F27/28 , H01L23/522 , H01F27/24 , H01F1/147 , H01F1/14 , H01L49/02
CPC分类号： H01L23/5227 , H01F1/14 , H01F1/14708 , H01F1/14766 , H01F17/0013 , H01F27/24 , H01F27/2804 , H01F41/046 , H01F2017/0066 , H01F2027/2809 , H01L28/10 , H01L2924/0002 , H01L2924/00
摘要： Magnetic core inductors implemented on integrated circuits and methods for fabricating such magnetic core inductors are disclosed. An exemplary magnetic core inductor includes a bottom magnetic plate that includes a center portion and first, second, third, and fourth extension portions extending from the center portion. The exemplary magnetic core inductor includes an interlayer dielectric layer disposed over the bottom magnetic plate, and within the interlayer dielectric layer, first, second, third, and fourth via trenches extending above a respective one of the first, second, third, and fourth extension portions, and a fifth via trench extending above the center portion. The magnetic core inductor further includes a stacked-ring inductor coil including a plurality of inductor rings surrounding the fifth via trench and a top magnetic plate including a center portion and first, second, third, and fourth extension portions extending from the center portion.

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