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1. 发明授权

US09806161B1 Integrated circuit structure having thin gate dielectric device and thick gate dielectric device 有权
公开(公告)号：US09806161B1
公开(公告)日：2017-10-31
申请号：US15092910
申请日：2016-04-07
申请人： GLOBALFOUNDRIES INC.
发明人： Shahrukh A. Khan , Unoh Kwon , Shahab Siddiqui , Sean M. Polvino , Joseph F. Shepard, Jr.
IPC分类号： H01L29/423 , H01L21/311 , H01L29/51 , H01L21/033 , H01L21/84 , H01L21/027 , H01L21/8234 , H01L27/12
CPC分类号： H01L29/42364 , H01L21/0273 , H01L21/0332 , H01L21/28202 , H01L21/31133 , H01L21/31144 , H01L21/823431 , H01L21/823462 , H01L21/845 , H01L27/1207 , H01L29/511 , H01L29/513 , H01L29/518 , H01L29/66545
摘要： One aspect of the disclosure relates to and integrated circuit structure and methods of forming the same. The integrated circuit structure may include: a thin gate dielectric device on a substrate, the thin gate dielectric device including: a first interfacial layer over a set of fins within the substrate, wherein the interfacial layer has a thickness of approximately 1.0 nanometers (nm) to approximately 1.2 nm; and a thick gate dielectric device on the substrate adjacent to the thin gate dielectric device, the thick gate dielectric device including: a second interfacial layer over the set of fins within the substrate; and a nitrided oxide layer over the second interfacial layer, wherein the nitrided oxide layer includes a thickness of approximately 3.5 nm to approximately 5.0 nm.

2. 发明申请

US20170294519A1 INTEGRATED CIRCUIT STRUCTURE HAVING THIN GATE DIELECTRIC DEVICE AND THICK GATE DIELECTRIC DEVICE 有权
公开(公告)号：US20170294519A1
公开(公告)日：2017-10-12
申请号：US15092910
申请日：2016-04-07
申请人： GLOBALFOUNDRIES INC.
发明人： Shahrukh A. Khan , Unoh Kwon , Shahab Siddiqui , Sean M. Polvino , Joseph F. Shepard, JR.
IPC分类号： H01L29/423 , H01L21/027 , H01L29/51 , H01L21/8234 , H01L21/033 , H01L27/12 , H01L21/84 , H01L21/311
CPC分类号： H01L29/42364 , H01L21/0273 , H01L21/0332 , H01L21/28202 , H01L21/31133 , H01L21/31144 , H01L21/823431 , H01L21/823462 , H01L21/845 , H01L27/1207 , H01L29/511 , H01L29/513 , H01L29/518 , H01L29/66545
摘要： One aspect of the disclosure relates to and integrated circuit structure and methods of forming the same. The integrated circuit structure may include: a thin gate dielectric device on a substrate, the thin gate dielectric device including: a first interfacial layer over a set of fins within the substrate, wherein the interfacial layer has a thickness of approximately 1.0 nanometers (nm) to approximately 1.2 nm; and a thick gate dielectric device on the substrate adjacent to the thin gate dielectric device, the thick gate dielectric device including: a second interfacial layer over the set of fins within the substrate; and a nitrided oxide layer over the second interfacial layer, wherein the nitrided oxide layer includes a thickness of approximately 3.5 nm to approximately 5.0 nm.

3. 发明授权

US09589806B1 Integrated circuit with replacement gate stacks and method of forming same 有权
标题翻译：具有更换栅极堆叠的集成电路及其形成方法
公开(公告)号：US09589806B1
公开(公告)日：2017-03-07
申请号：US14886424
申请日：2015-10-19
申请人： GLOBALFOUNDRIES Inc.
发明人： Ruqiang Bao , Unoh Kwon , Huihang Dong , John A. Fitzsimmons
IPC分类号： H01L21/28 , H01L21/283 , H01L21/8238 , H01L27/092 , H01L29/49
CPC分类号： H01L21/283 , H01L21/823828 , H01L21/823842 , H01L27/092 , H01L29/4966 , H01L29/66545
摘要： An IC structure including: a first replacement gate stack for the pFET, the first replacement gate stack including: an interfacial layer in a first opening in the dielectric layer; a high-k layer over the interfacial layer in the first opening; a pFET work function metal layer over the high-k layer in the first opening; and a first gate electrode layer over the pFET work function metal layer and substantially filling the first opening; and a second replacement gate stack for the nFET, the second gate stack laterally adjacent to the first gate stack and including: the interfacial layer in a second opening in the dielectric layer; the high-k layer over the interfacial layer in the second opening; a nFET work function metal layer over the high-k layer in the second opening; and a second gate electrode layer over the nFET work function metal layer and substantially filling the second opening.
摘要翻译：一种IC结构，包括：用于pFET的第一替换栅极堆叠，所述第一替换栅极堆叠包括：在所述介电层中的第一开口中的界面层; 在第一开口的界面层上的高k层; 在第一开口中的高k层上的pFET功函数金属层; 以及在pFET功函数金属层上方的基本上填充第一开口的第一栅极电极层; 以及用于nFET的第二替代栅极堆叠，所述第二栅极堆叠横向邻近所述第一栅极堆叠并且包括：所述介电层中的第二开口中的界面层; 在第二开口的界面层上的高k层; 在第二开口的高k层上的nFET功函数金属层; 以及在nFET功函数金属层上方的第二栅电极层，并基本上填充第二开口。

4. 发明授权

US09397199B1 Methods of forming multi-Vt III-V TFET devices 有权
标题翻译：形成多Vt III-V TFET器件的方法
公开(公告)号：US09397199B1
公开(公告)日：2016-07-19
申请号：US14992209
申请日：2016-01-11
申请人： GLOBALFOUNDRIES INC.
发明人： Unoh Kwon , Siddarth A. Krishnan , Vijay Narayanan , Jeffrey Sleight
IPC分类号： H01L21/76 , H01L29/66 , H01L21/762 , H01L21/268 , H01L29/51 , H01L21/02 , H01L21/306 , H01L21/28
CPC分类号： H01L29/66795 , H01L21/02252 , H01L21/02351 , H01L21/2686 , H01L21/28185 , H01L21/30604 , H01L21/76224 , H01L21/823418 , H01L21/82345 , H01L21/823462 , H01L21/8252 , H01L27/0605 , H01L27/088 , H01L29/20 , H01L29/511 , H01L29/513 , H01L29/517 , H01L29/66356 , H01L29/7391
摘要： The disclosure generally relates to a method for forming multiple III-V Tunnel Field-Effect Transistors (III-V TFETs) microchips in which each TFET has a different threshold voltage (Vt) or work-function. In one embodiment of the disclosure, four TFETs are formed on a substrate. Each TFET has a source, drain and a gate electrode. Each gate electrode is then processed independently to provide a substantially different threshold voltage. Each TFET will have an intrinsic channel.
摘要翻译：本发明一般涉及用于形成多个III-V隧道场效应晶体管（III-V TFET）微芯片的方法，其中每个TFET具有不同的阈值电压（Vt）或工作功能。在本公开的一个实施例中，在衬底上形成四个TFET。每个TFET都有源极，漏极和栅极。然后，每个栅极电极被独立地处理以提供基本上不同的阈值电压。每个TFET将具有固有通道。

5. 发明授权

US09397177B2 Variable length multi-channel replacement metal gate including silicon hard mask 有权
标题翻译：可变长度多通道替代金属栅极，包括硅硬掩模
公开(公告)号：US09397177B2
公开(公告)日：2016-07-19
申请号：US14088462
申请日：2013-11-25
申请人： GLOBALFOUNDRIES INC.
发明人： Michael P. Chudzik , Siddarth A. Krishnan , Unoh Kwon
IPC分类号： H01L29/78 , H01L27/088 , H01L29/423 , H01L27/092 , H01L21/8238 , H01L29/49 , H01L21/3213 , H01L21/28 , H01L29/51 , H01L29/66 , H01L21/321
CPC分类号： H01L29/42376 , H01L21/28088 , H01L21/3212 , H01L21/32139 , H01L21/823807 , H01L21/82385 , H01L27/0922 , H01L29/4966 , H01L29/517 , H01L29/66545
摘要： A method of forming a semiconductor device includes forming first and second semiconductor structures on a semiconductor substrate. The first semiconductor structure includes a first gate channel region having a first gate length, and the second semiconductor structure including a second gate channel region having a second gate length that is greater than the first gate length. The method further includes depositing a work function metal layer in each of a first gate void formed at the first gate channel region and a second gate void formed at the second gate channel region. The method further includes depositing a semiconductor masking layer on the work function metal layer, and simultaneously etching the silicon masking layer located at the first and second gate channel regions to re-expose the first and second gate voids. A low-resistive metal is deposited in the first and second gate voids to form low-resistive metal gate stacks.
摘要翻译：形成半导体器件的方法包括在半导体衬底上形成第一和第二半导体结构。第一半导体结构包括具有第一栅极长度的第一栅极沟道区，并且第二半导体结构包括具有大于第一栅极长度的第二栅极长度的第二栅极沟道区。该方法还包括在第一栅极沟道区域中形成的第一栅极空隙和形成在第二栅极沟道区域处的第二栅极空穴中沉积功函数金属层。该方法还包括在功函数金属层上沉积半导体掩模层，同时蚀刻位于第一和第二栅极沟道区的硅掩模层，以重新暴露第一和第二栅极空隙。在第一和第二栅极空隙中沉积低电阻金属以形成低电阻金属栅极叠层。

6. 发明授权

US10170373B2 Methods for making robust replacement metal gates and multi-threshold devices in a soft mask integration scheme 有权
公开(公告)号：US10170373B2
公开(公告)日：2019-01-01
申请号：US14495170
申请日：2014-09-24
申请人： GLOBALFOUNDRIES INC.
发明人： Balaji Kannan , Rekha Rajaram , Unoh Kwon
IPC分类号： H01L21/8238
摘要： A method of fabricating advanced multi-threshold field effect transistors using a replacement metal gate process. A first method includes thinning layers composed of multilayer film stacks and incorporating a portion of the remaining thinned film in some transistors. A second method includes patterning dopant materials for a high-k dielectric by using thinning layers composed of multilayer thin film stacks, or in other embodiments, by a single thinning layer.

7. 发明申请

US20170263707A1 EXPITAXIALLY REGROWN HETEROSTRUCTURE NANOWIRE LATERAL TUNNEL FIELD EFFECT TRANSISTOR 有权
公开(公告)号：US20170263707A1
公开(公告)日：2017-09-14
申请号：US15600837
申请日：2017-05-22
申请人： GLOBALFOUNDRIES INC.
发明人： Siddarth A. Krishnan , Unoh Kwon , Vijay Narayanan , Jeffrey W. Sleight
IPC分类号： H01L29/06 , H01L29/423 , H01L29/66 , H01L29/417
CPC分类号： H01L29/0673 , H01L29/083 , H01L29/165 , H01L29/205 , H01L29/41758 , H01L29/42356 , H01L29/45 , H01L29/458 , H01L29/66356 , H01L29/66469 , H01L29/66553 , H01L29/7391 , H01L29/775
摘要： After forming a buried nanowire segment surrounded by a gate structure located on a substrate, an epitaxial source region is grown on a first end of the buried nanowire segment while covering a second end of the buried nanowire segment and the gate structure followed by growing an epitaxial drain region on the second end of the buried nanowire segment while covering the epitaxial source region and the gate structure. The epitaxial source region includes a first semiconductor material and dopants of a first conductivity type, while the epitaxial drain region includes a first semiconductor material different from the first semiconductor material and dopants of a second conductivity type opposite the first conductivity type.

8. 发明授权

US09691662B2 Field effect transistors having multiple effective work functions 有权
公开(公告)号：US09691662B2
公开(公告)日：2017-06-27
申请号：US15338894
申请日：2016-10-31
申请人： GLOBALFOUNDRIES INC.
发明人： Takashi Ando , Min Dai , Balaji Kannan , Siddarth A. Krishnan , Unoh Kwon
IPC分类号： H01L21/8234 , H01L29/49 , H01L21/8238 , H01L27/092 , H01L21/324 , H01L27/088 , H01L29/78
CPC分类号： H01L21/823412 , H01L21/324 , H01L21/823431 , H01L21/82345 , H01L21/823462 , H01L21/823842 , H01L27/088 , H01L27/0886 , H01L27/092 , H01L27/0924 , H01L29/4966 , H01L29/785
摘要： Selective deposition of a silicon-germanium surface layer on semiconductor surfaces can be employed to provide two types of channel regions for field effect transistors. Anneal of an adjustment oxide material on a stack of a silicon-based gate dielectric and a high dielectric constant (high-k) gate dielectric can be employed to form an interfacial adjustment oxide layer contacting a subset of channel regions. Oxygen deficiency can be induced in portions of the high-k dielectric layer overlying the interfacial adjustment oxide layer by deposition of a first work function metallic material layer and a capping layer and a subsequent anneal. Oxygen deficiency can be selectively removed by physically exposing portions of the high-k dielectric layer. A second work function metallic material layer and a gate conductor layer can be deposited and planarized to form gate electrodes that provide multiple effective work functions.

9. 发明申请

US20170110539A1 EXPITAXIALLY REGROWN HETEROSTRUCTURE NANOWIRE LATERAL TUNNEL FIELD EFFECT TRANSISTOR 有权
公开(公告)号：US20170110539A1
公开(公告)日：2017-04-20
申请号：US14887572
申请日：2015-10-20
申请人： GLOBALFOUNDRIES INC.
发明人： Siddarth A. Krishnan , Unoh Kwon , Vijay Narayanan , Jeffrey W. Sleight
IPC分类号： H01L29/06 , H01L29/775 , H01L29/66 , H01L29/417 , H01L29/423
CPC分类号： H01L29/0673 , H01L29/083 , H01L29/165 , H01L29/205 , H01L29/41758 , H01L29/42356 , H01L29/45 , H01L29/458 , H01L29/66356 , H01L29/66469 , H01L29/66553 , H01L29/7391 , H01L29/775
摘要： After forming a buried nanowire segment surrounded by a gate structure located on a substrate, an epitaxial source region is grown on a first end of the buried nanowire segment while covering a second end of the buried nanowire segment and the gate structure followed by growing an epitaxial drain region on the second end of the buried nanowire segment while covering the epitaxial source region and the gate structure. The epitaxial source region includes a first semiconductor material and dopants of a first conductivity type, while the epitaxial drain region includes a first semiconductor material different from the first semiconductor material and dopants of a second conductivity type opposite the first conductivity type.

10. 发明授权

US09524986B2 Trapping dislocations in high-mobility fins below isolation layer 有权
标题翻译：在隔离层下方的高迁移率翅片中捕获位错
公开(公告)号：US09524986B2
公开(公告)日：2016-12-20
申请号：US14315362
申请日：2014-06-26
申请人： GLOBALFOUNDRIES INC.
发明人： Michael P. Chudzik , Ramachandra Divakaruni , Judson R. Holt , Arvind Kumar , Unoh Kwon
IPC分类号： H01L21/02 , H01L27/12 , H01L29/78 , H01L29/66 , H01L21/84 , H01L21/306 , H01L21/311 , H01L29/16 , H01L21/3105
CPC分类号： H01L27/1207 , H01L21/0243 , H01L21/02529 , H01L21/02532 , H01L21/02543 , H01L21/02546 , H01L21/02639 , H01L21/30604 , H01L21/31053 , H01L21/31111 , H01L21/845 , H01L27/1211 , H01L29/16 , H01L29/66795 , H01L29/7851
摘要： The present invention relates generally to semiconductor devices and more particularly, to a structure and method of forming a high-mobility fin field effect transistor (finFET) fin in a silicon semiconductor on insulator (SOI) substrate by trapping crystalline lattice dislocations that occur during epitaxial growth in a recess formed in a semiconductor layer. The crystalline lattice dislocations may remain trapped below a thin isolation layer, thereby reducing device thickness and the need for high-aspect ratio etching and fin formation.
摘要翻译：本发明一般涉及半导体器件，更具体地说，涉及通过捕获外延期间发生的晶格位错而在绝缘体上硅绝缘体（SOI）衬底上形成高迁移率鳍状场效应晶体管（finFET）鳍的结构和方法在半导体层中形成的凹部中生长。结晶晶格位错可以保留在薄的隔离层下方，从而减少器件厚度以及高纵横比蚀刻和鳍形成的需要。

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