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1. 发明申请

US20150129933A1 TUCK STRATEGY IN TRANSISTOR MANUFACTURING FLOW 有权
标题翻译：晶闸管制造流程中的TUCK策略
公开(公告)号：US20150129933A1
公开(公告)日：2015-05-14
申请号：US14076562
申请日：2013-11-11
申请人： GLOBAL FOUNDRIES Inc.
发明人： Robert Lutz
IPC分类号： H01L29/78 , H01L29/66 , H01L21/762
CPC分类号： H01L29/7848 , H01L21/76224 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L29/0692 , H01L29/66568 , H01L29/66636 , H01L29/7846
摘要： When forming field effect transistors with a semiconductor alloy layer, e.g., SiGe, embedded in the source/drain regions, a strategy called tucking has been developed in order to improve formation of the semiconductor alloy layer. An improved tucking strategy is hereby proposed, wherein the interface between the isolation region and the active region is not straight, but it rather defines an indentation, so that the active region protrudes into the isolation region in correspondence to the indentation. A gate is then formed on the surface of the device in such a way that a portion of the indentation is covered by the gate. An etching process is then performed, during which the gate acts as a screen. The etching thus gives rise to a cavity defined by a sidewall comprising portions exposing silicon, alternated to portions exposing the dielectric material of the isolation region.
摘要翻译：当用半导体合金层（例如嵌入在源/漏区中的SiGe）形成场效应晶体管时，已经开发了一种称为折叠的策略，以便改善半导体合金层的形成。因此，提出了一种改进的折叠策略，其中隔离区域和有源区域之间的界面不是直的，而是限定了凹陷，使得有源区域对应于凹陷突出到隔离区域中。然后在装置的表面上形成栅极，使得凹陷的一部分被栅极覆盖。然后执行蚀刻处理，在该过程期间，栅极用作屏幕。因此蚀刻产生由侧壁限定的空腔，该侧壁包括暴露硅的部分，交替地暴露隔离区的电介质材料的部分。

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