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1. 发明申请

US20150371898A1 INTEGRATED CIRCUITS INCLUDING MODIFIED LINERS AND METHODS FOR FABRICATING THE SAME 有权
标题翻译：集成电路，包括修改内线及其制作方法
公开(公告)号：US20150371898A1
公开(公告)日：2015-12-24
申请号：US14311457
申请日：2014-06-23
申请人： GLOBAL FOUNDRIES, Inc.
发明人： ERROL TODD RYAN , Xunyuan Zhang
IPC分类号： H01L21/768 , H01L23/532
CPC分类号： H01L23/53238 , H01L21/7682 , H01L21/76843 , H01L21/76853 , H01L21/76855 , H01L21/76856 , H01L21/76858 , H01L21/76868 , H01L2924/0002 , H01L2924/00
摘要： Integrated circuits and methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes contacting a liner that is disposed adjacent to a porous interlayer dielectric (ILD) layer of dielectric material with a selectively reactive gas at reaction conditions. A portion of the liner is reacted with the selectively reactive gas to form a converted expanded portion that is disposed between a remaining portion of the liner and the porous ILD layer.
摘要翻译：提供了用于制造集成电路的集成电路和方法。在一个示例中，制造集成电路的方法包括在反应条件下使与介电材料的多孔层间电介质层（ILD）层邻近设置的选择性反应气体接触。衬垫的一部分与选择性反应气体反应以形成转换的膨胀部分，其设置在衬垫的剩余部分和多孔ILD层之间。

2. 发明申请

US20150137271A1 METHODS OF FORMING GATE STRUCTURES FOR SEMICONDUCTOR DEVICES USING A REPLACEMENT GATE TECHNIQUE AND THE RESULTING DEVICES 有权
标题翻译：使用替换门技术和结果设备形成半导体器件的门结构的方法
公开(公告)号：US20150137271A1
公开(公告)日：2015-05-21
申请号：US14081019
申请日：2013-11-15
申请人： GLOBAL FOUNDRIES Inc.
发明人： Xiuyu Cai , Xunyuan Zhang
IPC分类号： H01L29/66 , H01L29/51 , H01L29/78
CPC分类号： H01L29/66545 , H01L29/66795 , H01L29/785
摘要： One method disclosed herein includes, among other things, performing a process operation on an exposed surface of a substrate so as to form an H-terminated silicon surface, selectively forming a sacrificial material layer within a replacement gate cavity but not on the H-terminated silicon surface, forming a high-k layer of insulating material within the replacement gate cavity above the H-terminated silicon surface and laterally between first spaced-apart portions of the sacrificial material layer, and forming a work-function adjusting material layer in the gate cavity, wherein the work-function adjusting material layer has a substantially planar upper surface that extends between second spaced-apart portions of the sacrificial material layer formed on the sidewall spacers.
摘要翻译：本文公开的一种方法包括在衬底的暴露表面上执行处理操作以形成H端接的硅表面，在置换栅腔内选择性地形成牺牲材料层，但不在H端接硅表面，在H端接的硅表面上方的置换栅腔内形成高k层绝缘材料，并在牺牲材料层的第一间隔开的部分之间横向地形成绝缘材料的高k层，并在栅极中形成功函数调节材料层空腔，其中所述功函调整材料层具有在形成在所述侧壁间隔物上的所述牺牲材料层的第二间隔开的部分之间延伸的基本平坦的上表面。

3. 发明申请

US20150235957A1 INTEGRATED CIRCUITS WITH IMPROVED CONTACT STRUCTURES 有权
标题翻译：具有改进接触结构的集成电路
公开(公告)号：US20150235957A1
公开(公告)日：2015-08-20
申请号：US14695965
申请日：2015-04-24
申请人： GLOBAL FOUNDRIES, Inc.
发明人： Xunyuan Zhang , Xuan Lin , Vimal Kamineni
IPC分类号： H01L23/532 , H01L23/528
CPC分类号： H01L23/53266 , H01L21/28562 , H01L21/31144 , H01L21/32134 , H01L21/76814 , H01L21/76843 , H01L21/76849 , H01L23/485 , H01L23/528 , H01L23/53209 , H01L23/53228 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： Integrated circuits with improved contact structures are provided. In an exemplary embodiment, an integrated circuit includes a semiconductor substrate disposed with a device therein and/or thereon. The integrated circuit includes a contact structure in electrical contact with the device. The contact structure includes a plug metal and a barrier layer, and the barrier layer is selected from fluorine-free tungsten (FFW), tungsten carbide, and tungsten nitride. The integrated circuit further includes a dielectric material overlying the semiconductor substrate. Also, the integrated circuit includes an interconnect formed within the dielectric material and in electrical contact with the contact structure.
摘要翻译：提供了具有改进的接触结构的集成电路。在示例性实施例中，集成电路包括在其中和/或其上设置有设备的半导体衬底。集成电路包括与器件电接触的接触结构。接触结构包括插塞金属和阻挡层，阻挡层选自无氟钨（FFW），碳化钨和氮化钨。集成电路还包括覆盖半导体衬底的电介质材料。此外，集成电路包括形成在电介质材料内并与接触结构电接触的互连。

4. 发明授权

US08609531B1 Methods of selectively forming ruthenium liner layer 有权
标题翻译：选择性地形成钌衬层的方法
公开(公告)号：US08609531B1
公开(公告)日：2013-12-17
申请号：US13787384
申请日：2013-03-06
申请人： Global Foundries Inc.
发明人： Xunyuan Zhang
IPC分类号： H01L21/4763
CPC分类号： H01L23/53238 , H01L21/76831 , H01L21/76843 , H01L21/76846 , H01L21/76855 , H01L21/76865 , H01L2924/0002 , H01L2924/00
摘要： One method includes forming a metal-containing material layer in a trench/via formed in a layer of insulating material, forming a sacrificial material layer above the metal-containing material layer to over-fill the trench/via with the sacrificial material, performing at least one process operation to remove portions of the metal-containing material layer and the sacrificial material layer positioned above an upper surface of the layer of insulating material and outside of the trench/via, removing the sacrificial material from within the trench/via to expose the metal-containing material layer positioned within the trench/via, selectively forming a material layer comprising a noble metal on the exposed metal-containing material without forming the material layer on the layer of insulating material, performing an anneal process to convert the metal-containing material layer into a metal-based silicate based barrier layer and forming a conductive copper structure in at least the trench/via above the material layer comprising the noble metal.
摘要翻译：一种方法包括在形成在绝缘材料层中的沟槽/通孔中形成含金属的材料层，在含金属材料层上方形成牺牲材料层，以用牺牲材料过度填充沟槽/通孔，在去除位于绝缘材料层的上表面上方和沟槽/通孔外部的含金属材料层和牺牲材料层的部分的至少一个处理操作，从沟槽/通孔内去除牺牲材料以暴露定位在沟槽/通孔内的含金属的材料层，在暴露的含金属材料上选择性地形成包含贵金属的材料层，而不在绝缘材料层上形成材料层，执行退火工艺以将金属 - 至少在沟槽/ v中形成导电铜结构 ia在包含贵金属的材料层之上。

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