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1. 发明授权

US07694052B2 Processing apparatus and processing module 失效
标题翻译：处理装置和处理模块
公开(公告)号：US07694052B2
公开(公告)日：2010-04-06
申请号：US11979270
申请日：2007-10-31
申请人： Fuyuta Sato , Naoki Fukuda
发明人： Fuyuta Sato , Naoki Fukuda
IPC分类号： G06F13/00
CPC分类号： G06F12/084 , G06F15/167 , G06F2212/1056
摘要： A processing apparatus has a master processing module and a plurality of slave processing modules. The master processing module has a master recording unit and a slave recording unit recording part of the data recorded in the master recording unit. The slave processing modules access the master processing module when it is necessary to access the data recorded in the master recording unit. When the data to be accessed from one slave processing module is recorded in the slave recording unit, the master processing module transmits the data to be accessed, from the slave recording unit to the one slave processing module. In the processing apparatus such as a base transceiver station communicating with transceivers such as mobile telephones, a reduction in the overall cost of the apparatus and an efficient internal communication are realized, and the overall processing time is reduced.
摘要翻译：处理装置具有主处理模块和多个从属处理模块。主处理模块具有记录主记录单元中记录的数据的一部分的主记录单元和从属记录单元。当需要访问主记录单元中记录的数据时，从属处理模块访问主处理模块。当从一个从属处理模块要访问的数据被记录在从属记录单元中时，主处理模块将从从属记录单元向一个从属处理模块发送要访问的数据。在与诸如移动电话的收发器进行通信的基站收发台等处理装置中，实现了设备的整体成本的降低和有效的内部通信，并且整体处理时间减少。

2. 发明申请

US20080256277A1 Processing apparatus and processing module 失效
标题翻译：处理装置和处理模块
公开(公告)号：US20080256277A1
公开(公告)日：2008-10-16
申请号：US11979270
申请日：2007-10-31
申请人： Fuyuta Sato , Naoki Fukuda
发明人： Fuyuta Sato , Naoki Fukuda
IPC分类号： G06F13/18
CPC分类号： G06F12/084 , G06F15/167 , G06F2212/1056
摘要： A processing apparatus has a master processing module and a plurality of slave processing modules. The master processing module has a master recording unit and a slave recording unit recording part of the data recorded in the master recording unit. The slave processing modules access the master processing module when it is necessary to access the data recorded in the master recording unit. When the data to be accessed from one slave processing module is recorded in the slave recording unit, the master processing module transmits the data to be accessed, from the slave recording unit to the one slave processing module. In the processing apparatus such as a base transceiver station communicating with transceivers such as mobile telephones, a reduction in the overall cost of the apparatus and an efficient internal communication are realized, and the overall processing time is reduced.
摘要翻译：处理装置具有主处理模块和多个从属处理模块。主处理模块具有记录主记录单元中记录的数据的一部分的主记录单元和从属记录单元。当需要访问主记录单元中记录的数据时，从属处理模块访问主处理模块。当从一个从属处理模块要访问的数据被记录在从属记录单元中时，主处理模块将从从属记录单元向一个从属处理模块发送要访问的数据。在与诸如移动电话的收发器进行通信的基站收发台等处理装置中，实现了设备的整体成本的降低和有效的内部通信，并且整体处理时间减少。

3. 发明授权

US09032008B2 Communication device, reception data length determination method, multiple determination circuit, and recording medium 有权
标题翻译：通信装置，接收数据长度确定方法，多重确定电路和记录介质
公开(公告)号：US09032008B2
公开(公告)日：2015-05-12
申请号：US12972574
申请日：2010-12-20
申请人： Fuyuta Sato
发明人： Fuyuta Sato
IPC分类号： H04L1/00 , G06F7/72 , G06F7/535
CPC分类号： G06F7/535 , G06F7/72 , H04L1/00
摘要： A communication device includes a storage unit to store quotients and remainders associated with multiplication values obtained by multiplying a specified integer number, which is expressed in a form of (2β+α) where β is a positive integer number and α is a positive integer number other than integral multiples of 2, respectively, the quotients and the remainders being obtained by dividing the multiplication values by 2β, respectively, a first unit to divide a dividend by 2βand calculate a quotient and a remainder, a second unit to obtain a quotient, which corresponds to the remainder from the storage unit, and a third unit to determine that the data length of the packet data is normal, when a combination of the quotient and the remainder calculated by the first unit is in the storage unit.
摘要翻译：通信装置包括存储单元，用于存储与乘法值相关联的乘数和余数，乘法值通过乘以指定的整数，以（2＆bgr; +α）的形式表示，其中＆bgr; 是正整数，α分别为2的积分倍数之外的正整数，商和余数分别通过将乘法值除以2＆bgr，获得第一单元，以将股息除以2＆bgr;以及计算商和余数，第二单元获得对应于来自存储单元的余数的商和第三单元，以确定分组数据的数据长度是正常的，当商和由第一单元计算的余数在存储单元中。

4. 发明授权

US08489665B2 Communication apparatus, method of checking received data size, multiple determining circuit, and multiple determination method 有权
标题翻译：通信装置，接收数据大小检查方法，多重判定电路，多重判定方法
公开(公告)号：US08489665B2
公开(公告)日：2013-07-16
申请号：US12360863
申请日：2009-01-28
申请人： Fuyuta Sato , Hideo Okawa
发明人： Fuyuta Sato , Hideo Okawa
IPC分类号： G06F7/38 , G06F7/44 , G06F7/42 , G06F7/52 , G06F7/50
CPC分类号： H04L1/00
摘要： A dividing unit sets an actual packet length transferred from a packet receiving section to a variable U, and then sets 2α to a variable V. If a positive number determining section determines that a subtraction result of subtracting a remainder N0 from a quotient M0, both found by dividing U by V, is a positive number, the dividing unit overwrites the subtraction result to U. The dividing unit repeats such operations of dividing the subtraction result by V, until the positive number determining section determines that the subtraction result of subtracting the remainder from the quotient, both found by dividing U by V, is a non-positive number. When the subtraction result becomes a non-positive number and the quotient and the remainder match, a packet length determining section determines that received data has a normal size, and notifies it to a discard determining section.
摘要翻译：分割单元将从分组接收部分传送的实际分组长度设置为变量U，然后将2alpha设置为变量V.如果正数确定部确定从商M0减去余数N0的减法结果，则两者通过将U除以V找到的是正数，分割单元将减法结果重写为U.分割单元重复将减法结果除以V的操作，直到正数确定部确定减去结果为止通过将U除以V所得到的商的余数是非正数。当减法结果变为非正数并且商和余数匹配时，分组长度确定部分确定接收到的数据具有正常大小，并将其通知丢弃确定部分。

5. 发明申请

US20080225858A1 Data transferring apparatus and information processing system 审中-公开
标题翻译：数据传输设备和信息处理系统
公开(公告)号：US20080225858A1
公开(公告)日：2008-09-18
申请号：US12074058
申请日：2008-02-29
申请人： Fuyuta Sato , Masayuki Furuta
发明人： Fuyuta Sato , Masayuki Furuta
IPC分类号： H04L12/56
CPC分类号： G06F13/1689
摘要： A data transferring unit performs hit determination on a cache memory based on a management table and a request from a CPU board. If requested data is not available in the cache memory, the data transferring unit reads and sequentially transfers the requested data from a shared memory in packets of optimum packet length stored in a time table in such a way that the previous packet is transferred while the next packet is read. In addition, the data transferring unit measures a packet transfer time. A packet-length optimizing unit varies, based on the packet transfer time calculated by the data transferring unit and data stored in the time table, an optimum packet length so that the difference between the packet transfer time and a packet read time is minimized.
摘要翻译：数据传送单元基于管理表和来自CPU板的请求，对高速缓存存储器进行命中判定。如果请求的数据在高速缓冲存储器中不可用，则数据传送单元以存储在时间表中的最佳分组长度的分组的顺序从所述共享存储器中读出并顺序地传送所请求的数据，使得先前分组被传送，而下一个分组数据包被读取。此外，数据传送单元测量分组传送时间。分组长度优化单元基于由数据传送单元计算的分组传送时间和存储在时间表中的数据而改变最优分组长度，使得分组传送时间和分组读取时间之间的差异最小化。

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