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1. 发明授权

US4096564A Data processing system with interrupt functions 失效
标题翻译：具有中断功能的数据处理系统
公开(公告)号：US4096564A
公开(公告)日：1978-06-20
申请号：US432871
申请日：1974-01-14
申请人： Fumiyuki Inose , Yuzo Kita
发明人： Fumiyuki Inose , Yuzo Kita
IPC分类号： G06F9/48 , G06F9/46 , G06F15/16 , G06F9/18
CPC分类号： G06F9/52
摘要： A data processing system comprises first and second arithmetic units for processing emergent tasks and non-emergent tasks, respectively, a memory for storing the data from the arithmetic units, and a control unit. The control unit selects either an interrupt task or a task being processed in response to the priority levels of the tasks. The first or second arithmetic unit is operated in response to whether a selected task is an emergent task or a non-emergent task.
摘要翻译：数据处理系统包括分别用于处理紧急任务和非紧急任务的第一和第二运算单元，用于存储来自算术单元的数据的存储器和控制单元。控制单元响应于任务的优先级来选择正在处理的中断任务或任务。响应于所选择的任务是紧急任务还是非紧急任务来操作第一或第二运算单元。

2. 发明授权

US4291241A Timing signal generating circuit 失效
标题翻译：定时信号发生电路
公开(公告)号：US4291241A
公开(公告)日：1981-09-22
申请号：US12708
申请日：1979-02-16
申请人： Koichi Mayama , Noboru Yamaguchi , Mamoru Sugie , Yuzo Kita , Shigeru Yoshizawa
发明人： Koichi Mayama , Noboru Yamaguchi , Mamoru Sugie , Yuzo Kita , Shigeru Yoshizawa
IPC分类号： H03K3/02 , G06F1/04 , G06F1/06 , G11C7/22 , G11C19/08 , H03K5/15
CPC分类号： G11C7/22 , G06F1/04 , G11C19/08 , G11C19/0875 , H03K5/15066
摘要： A timing signal generating circuit including a clock source which generates clock pulses of a predetermined period, a binary counter which divides the frequency of the clock pulses from the clock source by n, a logical array which decodes an output of the binary counter and which is composed of semiconductor elements and flip-flop circuits which are set or reset by outputs of the logical array in response to the clock pulses from the clock source with the outputs of the flip-flop circuits being used as timing signals.
摘要翻译：一种定时信号发生电路，包括产生预定周期的时钟脉冲的时钟源，将来自时钟源的时钟脉冲的频率除以n的二进制计数器，对二进制计数器的输出进行解码的逻辑阵列，由半导体元件和触发器电路组成，其由响应于来自时钟源的时钟脉冲而由逻辑阵列的输出设置或复位，触发器电路的输出用作定时信号。

3. 发明授权

US4511990A Digital processor with floating point multiplier and adder suitable for digital signal processing 失效
标题翻译：具有浮点乘法器和加法器的数字处理器适用于数字信号处理
公开(公告)号：US4511990A
公开(公告)日：1985-04-16
申请号：US311680
申请日：1981-10-15
申请人： Yoshimune Hagiwara , Shizuo Sugiyama , Narimichi Maeda , Osamu Yumoto , Takashi Akazawa , Masahito Kobayashi , Yasuhiro Kita , Yuzo Kita
发明人： Yoshimune Hagiwara , Shizuo Sugiyama , Narimichi Maeda , Osamu Yumoto , Takashi Akazawa , Masahito Kobayashi , Yasuhiro Kita , Yuzo Kita
IPC分类号： G06F7/00 , G06F5/01 , G06F7/50 , G06F7/57 , G06F7/76 , G06F17/10 , G06F7/48
CPC分类号： G06F7/483 , G06F5/012 , G06F7/485 , G06F2207/3856 , G06F7/49921
摘要： A signal processor having a wide dynamic range and which can process both data in the fixed point representation and data in the floating point representation by the use of a single floating-point arithmetic circuit is capable of processing digital signals, such as voice signals, at high speed and in real time. In addition, this signal processor is capable of executing data input/output operations with an external circuit in the data format of the fixed point representation and of performing internal operations in the floating point representation format. Further, conversion of an operational result from fixed point representation to floating point representation, and vice versa, can be performed internally in accordance with program instruction.
摘要翻译：具有宽动态范围并且可以通过使用单个浮点运算电路处理固定点表示中的数据和浮点表示中的数据的信号处理器能够处理诸如语音信号之类的数字信号高速和实时。此外，该信号处理器能够以固定点表示的数据格式的外部电路执行数据输入/输出操作，并且以浮点表示格式执行内部操作。此外，可以根据程序指令在内部将操作结果从固定点表示转换为浮点表示，反之亦然。

4. 发明授权

US4562424A Circuit for integrating analog signal and converting it into digital signal 失效
标题翻译：用于集成模拟信号并将其转换为数字信号的电路
公开(公告)号：US4562424A
公开(公告)日：1985-12-31
申请号：US517398
申请日：1983-07-26
申请人： Katsuaki Takagi , Yuzo Kita , Yoshimune Hagiwara , Shuichi Torii , Kazuyoshi Ogawa
发明人： Katsuaki Takagi , Yuzo Kita , Yoshimune Hagiwara , Shuichi Torii , Kazuyoshi Ogawa
IPC分类号： G01R22/00 , G01R21/00 , G01R21/127 , G01R21/133 , G06G7/186 , G01R21/06
CPC分类号： G01R21/133 , G01R21/00
摘要： An integrator circuit comprising reset means by which, when it is detected that an integrator output V.sub.p for an input analog signal coincides with a plus or minus reference value, the integral output is reset to the vicinity of the middle of the plus and minus reference values, in effect, without interrupting the integrating operation; a circuit which produces a pulse each time coincidence is detected; and a circuit which produces a direction signal indicating whether the coincidence results from an increase or a decrease of the integral input.The pulses produced in the state in which the direction signal is indicating an increase are counted up, and the pulses produced in the state in which the direction signal is indicating a decrease are counted down, whereby the precise integral value of the input analog signal can be detected.
摘要翻译：一种积分器电路，包括复位装置，当检测到输入模拟信号的积分器输出Vp与正或负参考值一致时，积分输出被复位到正和负参考值的中间附近实际上不中断整合操作; 检测每次产生脉冲的电路; 以及产生指示由积分输入的增加或减少引起的一致性的方向信号的电路。在方向信号指示增加的状态下产生的脉冲向上计数，并且在方向信号指示减小的状态下产生的脉冲向下计数，由此输入模拟信号的精确积分值被检测。

5. 发明授权

US4388612A Signal converter 失效
标题翻译：信号转换器
公开(公告)号：US4388612A
公开(公告)日：1983-06-14
申请号：US287824
申请日：1981-07-28
申请人： Katsuaki Takagi , Yuzo Kita
发明人： Katsuaki Takagi , Yuzo Kita
IPC分类号： H03M1/66 , H03M1/00 , H03M1/38 , H03K13/02
CPC分类号： H03M1/38
摘要： An analog-to-digital converter includes a capacitor array circuit for determining m upper bits of a digital output, which includes a plurality of capacitors having binary-weighted capacitance ratios and a plurality of switches and which is connected to an input terminal of a sampled analog voltage and a reference voltage source. A resistor string circuit is provided for determining n lower bits of the digital output, including a plurality of switches and which is connected to the capacitor array circuit. A voltage comparator compares an output voltage of the capacitor array circuit with the ground potential and successive approximation registers successively provide pulses for controlling the switches of the capacitor array circuit and the resistor string circuit in accordance with the output of the voltage comparator. A circuit generates timing pulses for controlling the operation of the successive approximation registers. The resistor string circuit applies voltages equal to i/2.sup.n (where i denotes a value expressed by the n lower bits of the digital output) and (2.sup.n -i)/2.sup.n of a reference voltage to the capacitor array circuit, and the capacitor array circuit operates so as to put the input analog signal into a digital signal in accordance with a linear input/output conversion characteristic.
摘要翻译：模数转换器包括用于确定数字输出的高位的电容器阵列电路，其包括具有二进制加权电容比的多个电容器和多个开关，并且连接到采样的输入端模拟电压和参考电压源。提供电阻串电路用于确定数字输出的n个较低位，包括多个开关，并连接到电容器阵列电路。电压比较器将电容器阵列电路的输出电压与地电位进行比较，并且逐次逼近寄存器根据电压比较器的输出，依次提供用于控制电容器阵列电路和电阻串电路的开关的脉冲。电路产生用于控制逐次逼近寄存器的操作的定时脉冲。电阻串电路向电容器阵列电路施加等于i / 2n（其中i表示数字输出的n个较低位的值）和参考电压的（2n-i）/ 2n）的电压，并且电容器阵列电路工作，以便根据线性输入/输出转换特性将输入模拟信号放入数字信号。

6. 发明授权

US4270220A Electronic tuning type television receiver 失效
标题翻译：电子调谐式电视接收机
公开(公告)号：US4270220A
公开(公告)日：1981-05-26
申请号：US70817
申请日：1979-08-29
申请人： Yoshimune Hagiwara , Terumi Sawase , Atsushi Takai , Yuzo Kita , Akira Honda
发明人： Yoshimune Hagiwara , Terumi Sawase , Atsushi Takai , Yuzo Kita , Akira Honda
IPC分类号： H03J5/02 , H04B1/26
CPC分类号： H03J5/0263
摘要： A television receiver of electronic tuning type employing a variable capacitance diode in a local oscillator of its tuning circuit, which comprises a memory storing a plurality of digital data indicative of tuning voltages corresponding to a plurality of channels respectively so that a tuning voltage corresponding to a selected channel can be applied to the variable capacitance diode in the tuning circuit, a D/A converter converting a digital data corresponding to a selected channel into an analog voltage to be supplied to the variable capacitance diode, and a tuning voltage control circuit which functions to sequentially modify, at a predetermined rate, the digital data of the selected channel read out from the memory until the tuning point is reached in the tuning circuit, and which applies sequentially such a signal to the D/A converter, whereby the tuning circuit can be tuned to the selected channel regardless of secular and other variations in the operating characteristic of the variable capacitance diode.
摘要翻译：一种在其调谐电路的本地振荡器中采用可变电容二极管的电子调谐型电视接收机，其包括分别存储表示与多个通道对应的调谐电压的多个数字数据的存储器，使得对应于所选择的通道可以应用于调谐电路中的可变电容二极管，D / A转换器将对应于所选通道的数字数据转换为要提供给可变电容二极管的模拟电压，以及调谐电压控制电路，其功能以预定速率顺序地修改从存储器读出的所选通道的数字数据，直到在调谐电路中达到调谐点，并且将该信号顺序地施加到D / A转换器，由此调谐电路可以调谐到所选择的频道，而不管v的操作特性的长期和其他变化可调电容二极管。

7. 发明授权

US4620292A Arithmetic logic unit for floating point data and/or fixed point data 失效
标题翻译：用于浮点数据和/或固定点数据的算术逻辑单元
公开(公告)号：US4620292A
公开(公告)日：1986-10-28
申请号：US700908
申请日：1985-02-12
申请人： Yoshimune Hagiwara , Shizuo Sugiyama , Narimichi Maeda , Osamu Yumoto , Takashi Akazawa , Masahito Kobayashi , Yasuhiro Kita , Yuzo Kita
发明人： Yoshimune Hagiwara , Shizuo Sugiyama , Narimichi Maeda , Osamu Yumoto , Takashi Akazawa , Masahito Kobayashi , Yasuhiro Kita , Yuzo Kita
IPC分类号： G06F7/00 , G06F5/01 , G06F7/50 , G06F7/57 , G06F7/76 , G06F17/10 , H03M7/24
CPC分类号： G06F7/483 , G06F5/012 , G06F7/485 , G06F2207/3856 , G06F7/49921
摘要： A signal processor having a wide dynamic range and which can process both data in the fixed point representation and data in the floating point representation by the use of a single floating-point arithmetic circuit is capable of processing digital signals, such as voice signals, at high speed and in real time. In addition, this signal processor includes an arithmetic logic unit for floating point data and/or fixed point data in which there is selectively provided a first pair of first and second floating point data which are to be subjected to an arithmetic operation, or a second pair of data consisting of third floating (fixed) point data which is to be converted to fixed (floating) point data and fourth floating point data which is a reference data for the conversion. If the first pair is selected the first and second pair of floating point data are subjected to the arithmetic operation. If the second pair is selected, the conversion of the fixed (floating) point data to floating (fixed) point data is effected by normalizing the third data with the value of the exponent part of the fourth data.

8. 发明授权

US4577154A Pulse width modulation circuit and integration circuit of analog product using said modulation circuit 失效
标题翻译：使用所述调制电路的模拟产品的脉宽调制电路和积分电路
公开(公告)号：US4577154A
公开(公告)日：1986-03-18
申请号：US517407
申请日：1983-07-26
申请人： Katsuaki Takagi , Yuzo Kita , Yoshimune Hagiwara , Kazuyoshi Ogawa , Hideo Hara
发明人： Katsuaki Takagi , Yuzo Kita , Yoshimune Hagiwara , Kazuyoshi Ogawa , Hideo Hara
IPC分类号： G01R22/00 , G01R21/127 , G06G7/161 , G06G7/186 , H03K7/06 , H03K7/08 , H03M1/50 , H03M1/82 , H03K5/05
CPC分类号： H03M1/82 , H03K7/08
摘要： A pulse width modulation circuit which can cancel the mean error of pulse width modulation with respect to time due to the offset voltage of a triangular wave signal and to the offset voltage of a comparator, by adding simple circuits to an existing pulse width modulation circuit. The invention relates also to an integration circuit of the product of two analog signals using the pulse width modulation circuit described above.The principle of the present invention combines a circuit for cancelling the offset of a triangular wave signal by inverting either the triangular wave signal with respect to an input signal or the input signal with respect to the triangular wave signal, in every predetermined period, with a circuit for eliminating the offset of a comparator by inverting the output of the comparator and replacing the input terminals of the comparator if the input signal is not inverted, or connecting the input terminal of the comparator as such if the input signal is inverted.
摘要翻译：一种脉冲宽度调制电路，通过将简单的电路加到现有的脉宽调制电路上，可以消除三角波信号的偏移电压和比较器的偏移电压相对于时间的脉冲宽度调制的平均误差。本发明还涉及使用上述脉冲宽度调制电路的两个模拟信号的乘积的积分电路。本发明的原理结合了用于消除三角波信号的偏移的电路，通过在每个预定周期内相对于三角波信号相对于输入信号或输入信号反转三角波信号，电路，用于通过反相比较器的输出来消除比较器的偏移，并且如果输入信号不被反相则替换比较器的输入端，或者如果输入信号反相则连接比较器的输入端。

9. 发明授权

US4290117A Memory device with circulating storage loops 失效
标题翻译：具有循环存储环路的存储器
公开(公告)号：US4290117A
公开(公告)日：1981-09-15
申请号：US13066
申请日：1979-02-21
申请人： Mamoru Sugie , Noboru Yamaguchi , Koichi Mayama , Yuzo Kita , Shigeru Yoshizawa , Nobuo Saito , Atsushi Asano
发明人： Mamoru Sugie , Noboru Yamaguchi , Koichi Mayama , Yuzo Kita , Shigeru Yoshizawa , Nobuo Saito , Atsushi Asano
IPC分类号： G11C11/14 , G11C19/08 , G11C29/00
CPC分类号： G11C29/86 , G11C19/0875
摘要： In a memory device which has a plurality of recirculating type storage loops and in which information of the same addresses of the respective storage loops can be read and written in parallel, a memory device wherein information representing whether or not the corresponding storage loop is a bad or defective loop is written in a specified address of each of the storage loops.
摘要翻译：在具有多个再循环型存储环路并且可以并行地读取和写入相应存储环路的相同地址的信息的存储装置中，存储装置，其中表示对应的存储环路是否为坏的信息或故障循环写入每个存储循环的指定地址。

10. 发明授权

US4592006A Adder for floating point data suitable for digital signal processing 失效
标题翻译：适用于数字信号处理的浮点数据加法器
公开(公告)号：US4592006A
公开(公告)日：1986-05-27
申请号：US700907
申请日：1985-02-12
申请人： Yoshimune Hagiwara , Shizuo Sugiyama , Narimichi Maeda , Osamu Yumoto , Takashi Akazawa , Masahito Kobayashi , Yasuhiro Kita , Yuzo Kita
发明人： Yoshimune Hagiwara , Shizuo Sugiyama , Narimichi Maeda , Osamu Yumoto , Takashi Akazawa , Masahito Kobayashi , Yasuhiro Kita , Yuzo Kita
IPC分类号： G06F7/00 , G06F5/01 , G06F7/50 , G06F7/57 , G06F7/76 , G06F17/10
CPC分类号： G06F7/483 , G06F5/012 , G06F7/485 , G06F2207/3856 , G06F7/49921
摘要： In an adder for floating point data, two floating point data are adjusted so that the exponent parts have the same value and the resulting adjusted mantissa parts are added. A first shift signal is generated on the basis of the result of the added mantissa parts and having a value necessary for normalization of the addition result, and a second shift signal is generated having a value equal to the difference between the adjusted exponent part of the floating point data and a minimum value predetermined for an exponent of any floating point data at which underflow occurs. The result of addition of the adjusted mantissa parts is shifted on the basis of said second shift signal or said first shift signal depending on whether or not an underflow occurs.

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