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1. 发明授权

US08275196B2 Image processing device and image processing method 失效
标题翻译：图像处理装置及图像处理方法
公开(公告)号：US08275196B2
公开(公告)日：2012-09-25
申请号：US13196463
申请日：2011-08-02
申请人： Fumio Yoshiya , Akihiro Oue , Masahiro Yamada
发明人： Fumio Yoshiya , Akihiro Oue , Masahiro Yamada
IPC分类号： G06K9/00
CPC分类号： H04N13/111
摘要： According to one embodiment, an image processing device includes a plurality of parallax image generators. Each of the parallax image generators is configured to generate a first image and a second image based on an input image and a parameter for setting a distance between viewpoints. There is a first parallax between the first image and the second image. The first parallax depends on the parameter for setting the distance between viewpoints. The input image is inputted to the parallax image generators in common. A plurality of parameters for setting the distance between viewpoints different from each other are inputted to the parallax image generators, respectively.
摘要翻译：根据一个实施例，图像处理装置包括多个视差图像生成器。每个视差图像生成器被配置为基于输入图像生成第一图像和第二图像，以及用于设置视点之间的距离的参数。在第一图像和第二图像之间存在第一视差。第一视差取决于设置视点之间距离的参数。输入图像被共同地输入到视差图像生成器。将用于设定彼此不同的视点之间的距离的多个参数分别输入到视差图像生成器。

2. 发明申请

US20100333103A1 INFORMATION PROCESSOR AND INFORMATION PROCESSING METHOD 审中-公开
标题翻译：信息处理器和信息处理方法
公开(公告)号：US20100333103A1
公开(公告)日：2010-12-30
申请号：US12795544
申请日：2010-06-07
申请人： Naomiki Kobayashi , Hiroki Iwahara , Jun Sato , Keisuke Yasui , Fumio Yoshiya , Keiko Watanabe , Jun Ohashi
发明人： Naomiki Kobayashi , Hiroki Iwahara , Jun Sato , Keisuke Yasui , Fumio Yoshiya , Keiko Watanabe , Jun Ohashi
IPC分类号： G06F9/50
CPC分类号： G06F9/5022 , G06F9/5016
摘要： According to one embodiment, an information processor includes a management module that manages a plurality of register areas in a host controller for processing data protected by copyright. The register areas store confidential information for copyright protection. The management module includes a use state management module and a release module. The use state management module manages use state information on whether the register areas are used by existing process tasks. When all the register areas are occupied by the existing process tasks and a new process task requests for the use of a register area to perform a process based on the confidential information, the release module releases a register area occupied by one of the existing process tasks according to the use state information to assign the register area to the new process task.
摘要翻译：根据一个实施例，信息处理器包括管理模块，管理主机控制器中的多个寄存器区域，以处理受版权保护的数据。注册区域存储着作权保护的机密信息。管理模块包括使用状态管理模块和释放模块。使用状态管理模块管理关于登记区域是否被现有的处理任务使用的使用状态信息。当所有寄存器区域被现有流程任务占用时，新的流程任务请求使用寄存器区域来执行基于机密信息的进程，释放模块释放由现有流程任务之一占用的寄存器区域根据使用状态信息将注册区域分配给新的进程任务。

3. 发明授权

US08386804B2 Semiconductor integrated device and method of testing semiconductor integrated device 有权
标题翻译：半导体集成器件及半导体集成器件测试方法
公开(公告)号：US08386804B2
公开(公告)日：2013-02-26
申请号：US12369699
申请日：2009-02-11
申请人： Fumio Yoshiya
发明人： Fumio Yoshiya
IPC分类号： G06F11/30 , G06F7/02
CPC分类号： G01R31/318533 , G06F21/72 , G09C1/00 , H04L9/0637 , H04L9/0894 , H04L2209/04 , H04L2209/12 , H04L2209/26
摘要： According to one embodiment, a semiconductor integrated device which stores secret data and is capable of operating in a test mode in which a scan test with respect to an internal circuit is executed, the semiconductor integrated device comprises a mode signal receiving module configured to receive a scan mode signal designating the test mode, a mask module configured to mask the secret data when the mode signal receiving module receives the scan mode signal, and an error detection module configured to detect presence or absence of error in the secret data and to store detection result in a first flip-flop.
摘要翻译：根据一个实施例，一种半导体集成装置，其存储秘密数据并且能够在执行相对于内部电路的扫描测试的测试模式下操作，所述半导体集成装置包括模式信号接收模块，其被配置为接收指定所述测试模式的扫描模式信号，掩模模块，被配置为当所述模式信号接收模块接收到所述扫描模式信号时掩蔽所述秘密数据;以及错误检测模块，被配置为检测所述秘密数据中是否存在错误并存储检测导致第一个触发器。

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