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1. 发明授权

US5301307A Microprocessor having waiting function 失效
标题翻译：微处理器具有等待功能
公开(公告)号：US5301307A
公开(公告)日：1994-04-05
申请号：US828214
申请日：1992-01-30
申请人： Fumio Murooka , Yuusuke Kajikawa , Kazuharu Date , Hiroshi Mikami , Shigeki Imai , Katsuhiro Masui
发明人： Fumio Murooka , Yuusuke Kajikawa , Kazuharu Date , Hiroshi Mikami , Shigeki Imai , Katsuhiro Masui
IPC分类号： G06F9/30 , G06F9/22 , G06F9/26
CPC分类号： G06F9/262
摘要： A microprocessor capable of executing a micro-instruction output from a micro-memory according to an address which corresponds to an instruction to be executed at a time when each time the microprocessor receives the address is provided. The microprocessor includes a unit (a T1 cycle signal generator, a T2 cycle signal generator, a TW cycle signal generator) for generating a control signal for a period of time corresponding to a period of time of a waiting signal at a time when the waiting signal is received from the outside, and a unit (a microcode read-only memory, a read-only memory address latch, a read-only memory output latch, an address control circuit, a multiplexer) connected to the control signal generating unit (the T1 cycle signal generator, the T2 cycle signal generator, the TW cycle signal generator) for holding an address supplied to the micro-memory for a period of time corresponding to a period of time of the control signal.
摘要翻译：能够根据与每当微处理器接收到地址时执行的指令对应的地址，从微存储器执行微指令输出的微处理器。微处理器包括一个单元（一个T1周期信号发生器，一个T2周期信号发生器，一个TW周期信号发生器），用于产生一个控制信号，该时间段对应于等待时间等待时间的一段时间信号从外部接收，以及连接到控制信号生成单元的单元（微代码只读存储器，只读存储器地址锁存器，只读存储器输出锁存器，地址控制电路，多路复用器） T1周期信号发生器，T2周期信号发生器，TW周期信号发生器），用于保持提供给微存储器的地址与控制信号的时间段相对应的时间段。

2. 发明授权

US5418933A Bidirectional tri-state data bus buffer control circuit for delaying direction switching at I/O pins of semiconductor integrated circuit 失效
标题翻译：双向三态数据总线缓冲控制电路，用于延迟半导体集成电路I / O引脚的方向切换
公开(公告)号：US5418933A
公开(公告)日：1995-05-23
申请号：US829472
申请日：1992-02-03
申请人： Kazuo Kimura , Takeshi Yoshii , Shigeki Imai , Katsuhiro Masui
发明人： Kazuo Kimura , Takeshi Yoshii , Shigeki Imai , Katsuhiro Masui
IPC分类号： G06F13/40 , H04L5/16 , G06F13/00 , G06F13/38
CPC分类号： G06F13/4072 , H04L5/16
摘要： A data bus control circuit is formed on a single semiconductor integrated circuit that includes input/output terminals for external data exchange and a plurality of functional blocks including a CPU. A bi-directional bus buffer buffers data sent over a data bus between the CPU and the input/output terminals. The signal propagation direction of the bus buffer is determined according to a logic level of a read control signal supplied from the CPU.
摘要翻译：数据总线控制电路形成在包括用于外部数据交换的输入/输出端子和包括CPU的多个功能块的单个半导体集成电路上。双向总线缓冲器缓冲通过CPU和输入/输出端子之间的数据总线发送的数据。总线缓冲器的信号传播方向根据从CPU提供的读取控制信号的逻辑电平来确定。

3. 发明授权

US5428528A Portable interactive game system between master/slave units containing detachable memories wherein a master unit downloads a master program to slave units respective detachable memories 失效
标题翻译：包含可拆卸存储器的主/从单元之间的便携式交互式游戏系统，其中主单元将主程序下载到各个可分离存储器的从单元
公开(公告)号：US5428528A
公开(公告)日：1995-06-27
申请号：US750865
申请日：1991-08-28
申请人： Norio Takenouchi , Setsunobu Wakamoto , Katsuhiro Masui
发明人： Norio Takenouchi , Setsunobu Wakamoto , Katsuhiro Masui
IPC分类号： G06F9/445 , A63F13/12 , G06F13/00 , G06F9/06
CPC分类号： A63F13/31 , A63F13/12 , A63F13/35 , A63F13/92 , A63F13/95 , A63F2300/204 , A63F2300/50
摘要： A communication processing system provided with one parent communication unit, at least one child communication unit, and at least one first detachable unit detachable from the at least one child unit, the system being operated in accordance with an operation program stored in a second detachable unit detachable from the parent unit, includes a transfer unit for transferring the operation program to the at least one child unit, a first storage unit for storing the operation program transferred from the parent unit by the transfer unit when the second detachable unit is mounted on the parent unit, the first storage unit being provided in the first detachable unit, and a second storage unit for storing a receiving program for receiving data sent from the parent unit, the second storage unit being provided in the first detachable unit. The first storage unit is provided in the first detachable unit. The second storage unit is provided in the first detachable unit.
摘要翻译：一种通信处理系统，具有一个母通信单元，至少一个子通信单元和至少一个可从所述至少一个子单元拆卸的第一可拆卸单元，所述系统根据存储在第二可拆卸单元中的操作程序操作可以从母单元拆卸，包括用于将操作程序传送到至少一个子单元的传送单元;第一存储单元，用于当第二可拆卸单元安装在主单元上时，存储由母单元从传送单元传送的操作程序所述第一存储单元设置在所述第一可拆卸单元中，以及第二存储单元，用于存储用于接收从所述母单元发送的数据的接收程序，所述第二存储单元设置在所述第一可拆卸单元中。第一存储单元设置在第一可拆卸单元中。第二存储单元设置在第一可拆卸单元中。

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