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    • 4. 发明授权
    • Connector for a camera
    • 相机连接器
    • US4970558A
    • 1990-11-13
    • US221614
    • 1988-07-20
    • Mutsuhide MatsudaMasao AoyagiHiroshi FurukawaMasami Shimizu
    • Mutsuhide MatsudaMasao AoyagiHiroshi FurukawaMasami Shimizu
    • G03B17/14H01R13/24
    • H01R13/2471G03B17/14
    • An optical accessory includes a bayonet mount attachable to a camera body side mount and accessory side connection terminals which contact the camera body side connecting terminals when the accessory side bayonet mount is attached to the camera body side bayonet mount. The accessory side connecting terminals have their end portions arranged to project in the direction of the optical axis behind the accessory side bayonet mount. In one preferred embodiment, the optical accessory further includes a member having a projection projecting in the direction of the optical axis behind the accessory side connecting terminals. The projection is positioned on the inner circumference side of the accessory side connecting terminals and is arranged near to the accessory side connection terminals. In another preferred embodiment, the end portions of the connecting terminals have plural height differences, and a contact seat also is provided for holding the accessory side connecting terminals. The contact seat has its rear side surface in the direction of the optical axis located at substantially the same height as the accessory side connecting terminals. The contact seat is fixed by a fastener in a radial direction relative to an inner circumference surface of the accessory side bayonet mount.
    • 5. 发明授权
    • Connector for a camera
    • 相机连接器
    • US4853725A
    • 1989-08-01
    • US271363
    • 1988-11-14
    • Mutsuhide MatsudaMasao AoyagiHiroshi FurukawaMasami Shimizu
    • Mutsuhide MatsudaMasao AoyagiHiroshi FurukawaMasami Shimizu
    • G03B17/14H01R13/24
    • H01R13/2471G03B17/14
    • A connector structure for a camera having bayonet mounts on the side of a camera body and on the side of an accessory, the camera body and the accessory being interconnected by rotating the mounts round relative to each other and being disconnected by reversely rotating the mounts. A group of contact pins is arranged at a camera body side connector to be slidingly brought into contact with a group of contact pins arranged at an accessory side connector by the rotational mounting action. The group of contact pins at the accessory side connector being in paired contact with the pins of the group of contact pins at the camera body side connector to permit communication between the camera body and the accessory upon completion of the mounting action. A first conductive member is arranged to be electrically connected in parallel with a first contact pin among the group of contact pins arranged at one of the connectors. The first contact pin coming into sliding contact with only one of the group of contact pins arranged at another of the connectors while the two mounts are rotated relative to each other. A second conductive member is arranged at the other of the connectors to abut on the first conductive member upon completion of the mounting action to be electrically connected in parallel to a second contact pin which is arranged at the other of the connectors and abuts the first contact pin upon completion of the mounting action.
    • 用于具有卡口的相机的连接器结构安装在相机主体的侧面上并且在附件的侧面上,照相机主体和附件通过相对于彼此旋转安装件而相互连接并通过反向旋转安装件而断开连接。 一组接触针布置在相机主体侧连接器处,以通过旋转安装动作滑动地与设置在附件侧连接器处的一组接触针接触。 在附件侧连接器处的一组接触销与照相机主体侧连接器处的接触销组的销成对接触,以在安装动作完成时允许照相机主体和附件之间的通信。 第一导电构件布置成在布置在连接器中的一个处的接触针组中与第一接触针并联电连接。 当两个安装座相对于彼此旋转时,第一接触销仅与布置在另一个连接器上的一组接触销中的一个滑动接触。 第二导电构件布置在另一个连接器处,以在安装动作完成时抵靠在第一导电构件上,以平行地电连接到布置在另一个连接器处并邻接第一接触件的第二接触销 在安装动作完成后,
    • 8. 发明授权
    • Semiconductor integrated circuit in in a carry computation network having a logic blocks which are dynamically reconfigurable
    • 携带计算网络中的半导体集成电路具有可动态重新配置的逻辑块
    • US08352533B2
    • 2013-01-08
    • US12332673
    • 2008-12-11
    • Hiroshi Furukawa
    • Hiroshi Furukawa
    • G06F7/57
    • G06F7/5443
    • There is provided a semiconductor integrated circuit including: a plurality of first logic blocks which are reconfigurable, the plurality of first logic blocks inputting data of a first bit width and performing computation; a first network connecting the plurality of first logic blocks in a dynamically reconfigurable manner; a plurality of second logic blocks inputting data of a second bit width different from the first bit width and performing computation; a second network connected to outputs of the plurality of second logic blocks; and a third network connecting a carry bit output of a computing unit included in the first logic block to an input of a computing unit included in the second logic block in a dynamically reconfigurable manner.
    • 提供了一种半导体集成电路,包括:多个可重新配置的第一逻辑块,多个第一逻辑块输入第一位宽的数据并执行计算; 以动态可重新配置的方式连接所述多个第一逻辑块的第一网络; 多个第二逻辑块,输入与第一位宽不同的第二位宽的数据,并执行计算; 连接到所述多个第二逻辑块的输出的第二网络; 以及以动态可重新配置的方式将包括在第一逻辑块中的计算单元的进位位输出连接到包括在第二逻辑块中的计算单元的输入的第三网络。
    • 10. 发明授权
    • Enhanced processor element structure in a reconfigurable integrated circuit device
    • 可重构集成电路设备中增强的处理器元件结构
    • US07734896B2
    • 2010-06-08
    • US11390131
    • 2006-03-28
    • Hiroshi Furukawa
    • Hiroshi Furukawa
    • G06F15/76
    • G06F15/8007
    • A reconfigurable integrated circuit device which converts an arbitrary calculation state dynamically, based on configuration data, includes a plurality of processor elements, each of which has an input terminal, an output terminal, a plurality of arithmetic units which are provided in parallel and each of which performs calculation processing in synchronous with a clock signal, and an intra-processor network which connects them in an arbitrary state; and an inter-processor network which connects between processor elements in an arbitrary state. Based on configuration data, the intra-processor network is reconfigurable to a desired connection state, and further, based on the configuration data, the inter-processor network is reconfigurable to a desired connection state.
    • 基于配置数据动态地转换任意计算状态的可重构集成电路装置包括多个处理器元件,每个处理器元件具有输入端子,输出端子,并行设置的多个运算单元, 其执行与时钟信号同步的计算处理和以任意状态连接它们的处理器内网络; 以及以任意状态连接处理器元件之间的处理器间网络。 基于配置数据,内部处理器网络可重新配置为期望的连接状态,并且此外,基于配置数据,处理器间网络可重新配置为期望的连接状态。