会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 10. 发明授权
    • Semiconductor integrated circuit device
    • 半导体集成电路器件
    • US07122868B2
    • 2006-10-17
    • US10781001
    • 2004-02-18
    • Takao Honda
    • Takao Honda
    • H01L29/72
    • G06F1/12H03K5/1506
    • To provide a semiconductor integrated circuit device that reduces charging and discharging currents flowing through clock tree synthesis, thereby reducing current consumption of entire circuits of the semiconductor integrated circuit device.In a semiconductor integrated circuit device including a clock synchronous type circuit that operates in synchronization with either of rising and falling edges flank of a reference clock and a plurality of clock buffer circuits for distributing the reference clock to the clock synchronous type circuit, each clock buffer circuit is constituted from a first transistor that drives a load at one of the edges flank of the reference clock with which the clock synchronous type circuit does not operate in synchronization and a second transistor that drives the load at the other edge flank of the reference clock. A gate width of the first transistor is set so that a change in the edge flank is slowed down, provided that a pulse waveform of the reference clock is not destroyed. A carrier type of the second transistor is different from the carrier type of the first transistor, and the second transistor is formed to have the gate width larger than the first transistor.
    • 提供一种降低通过时钟树合成流动的充电和放电电流的半导体集成电路器件,从而降低半导体集成电路器件的整个电路的电流消耗。 在包括与参考时钟侧面的上升沿和下降沿同步操作的时钟同步型电路以及用于将参考时钟分配给时钟同步型电路的多个时钟缓冲电路的半导体集成电路器件中,每个时钟缓冲器 电路由第一晶体管构成,该第一晶体管驱动时钟同步型电路不同步操作的参考时钟侧面的一侧边缘处的负载,以及驱动参考时钟的另一边缘处的负载的第二晶体管 。 设置第一晶体管的栅极宽度,使得边缘侧面的变化减慢,只要参考时钟的脉冲波形不被破坏。 第二晶体管的载体类型与第一晶体管的载流子类型不同,并且第二晶体管形成为具有大于第一晶体管的栅极宽度。