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1. 发明申请

US20040008060A1 Clock multiplication circuit 有权
标题翻译：时钟乘法电路
公开(公告)号：US20040008060A1
公开(公告)日：2004-01-15
申请号：US10606226
申请日：2003-06-26
申请人： FUJITSU LIMITED
发明人： Hideaki Watanabe
IPC分类号： H03B019/00
CPC分类号： H03L7/093 , H03L7/181
摘要： There is provided a clock multiplication circuit simple in configuration, easy to adjust the characteristics thereof, and capable of shortening lockup time. The clock multiplication circuit is a circuit for delivering an output clock signal at a frequency that is a multiple of the frequency of a reference clock signal as inputted. A counter of the circuit counts the number of rising edges of the output clock signal ST existing during a High level period of the reference clock signal SR, thereby delivering a count value CN. A subtracter subtracts the count value CN from a reference value BN, thereby delivering a difference value DN. An adder adds the difference value DN to a preceding integrated value IN, thereby calculating a new integrated value IN. A DA converter delivers the analog control voltage AV corresponding to the integrated value IN. A VCO delivers the output clock signal ST at a frequency corresponding to the analog control voltage AV. With the circuit, the frequency of the output clock signal ST is controlled such that DNnullBNnullCNnull0.
摘要翻译：提供了一种构造简单的时钟倍增电路，易于调整其特性，并且能够缩短锁定时间。时钟倍增电路是用于以输入的参考时钟信号的频率的倍数来传送输出时钟信号的电路。电路的计数器对参考时钟信号SR的高电平期间内存在的输出时钟信号ST的上升沿数进行计数，从而输出计数值CN。减法器从参考值BN中减去计数值CN，从而输出差值DN。加法器将差值DN加到先前的积分值IN，从而计算新的积分值IN。 DA转换器提供对应于积分值IN的模拟控制电压AV。 VCO以与模拟控制电压AV对应的频率输出输出时钟信号ST。利用电路，控制输出时钟信号ST的频率使得DN = BN-CN = 0。

2. 发明申请

US20040027181A1 Clock multiplying PLL circuit 审中-公开
标题翻译：时钟乘法PLL电路
公开(公告)号：US20040027181A1
公开(公告)日：2004-02-12
申请号：US10606225
申请日：2003-06-26
申请人： FUJITSU LIMITED
发明人： Hideaki Watanabe
IPC分类号： H03L007/06
CPC分类号： H03L7/0812 , H03L7/07 , H03L7/087 , H03L7/0891 , H03L7/199
摘要： The present invention provides a clock multiplying PLL circuit capable of suppressing jitters with a simple configuration and shortening a lockup time. The clock multiplying PLL circuit (1) comprises a VCO (40) for outputting an output clock signal (ST), first through n-th dividers (51 through 5n) for dividing the output clock signal (ST) and thereby outputting first through n-th divided signals (SD1 through SDn), a DLL (60) for generating first through n-th reference clock signals (SB1 through SBn) different in phase from one another using a reference clock signal (SR), and first through n-th phase comparators (11 through 1n) for comparing phases of i-th reference clock signals (SBi) and i-th divided signals (SDi) (where i: an integer of 1 to n). An oscillation frequency of the output clock signal (ST) of the VCO (40) changes based on the results of comparisons by the first through n-th phase comparators (11 through 1n).
摘要翻译：本发明提供一种能够以简单配置抑制抖动并缩短锁定时间的时钟倍增PLL电路。时钟倍增PLL电路（1）包括用于输出输出时钟信号（ST）的VCO（40），用于分频输出时钟信号（ST）的第一至第n分频器（51至5n），从而输出第一至第n 第一划分信号（SD1至SDn），用于使用参考时钟信号（SR）产生彼此不同相位的第一至第n参考时钟信号（SB1至SBn）的DLL（60）用于比较第i个参考时钟信号（SBi）和第i个分频信号（SDi）（其中i：1到n的整数）的相位的第三相位比较器（11至1n）。 VCO（40）的输出时钟信号（ST）的振荡频率根据第一〜第n相位比较器（11〜1n）的比较结果而变化。

3. 发明申请

US20040257119A1 Signal detection apparatus, signal detection method, signal transmission system, and computer readable program to execute signal transmission 有权
标题翻译：信号检测装置，信号检测方法，信号传输系统以及执行信号传输的计算机可读程序
公开(公告)号：US20040257119A1
公开(公告)日：2004-12-23
申请号：US10896967
申请日：2004-07-23
申请人： Fujitsu Limited
发明人： Hideaki Watanabe , Hiroko Haraguchi
IPC分类号： H03F003/45
CPC分类号： H04L25/0286 , H03F3/45237 , H03F2203/45466 , H03K5/08 , H03K5/19 , H03K5/2481 , H04L25/0272
摘要： In a differential output signal circuit suitable for restraining voltage overshooting/undershooting at differential output terminals due to lags in input signals and realizing stable and fast switching of differential input signals, a first differential pair of PMOS. transistors connected to a first current source and a second differential pair of NMOS transistors connected to a second current source are mutually connected at the differential output terminals, and a capacitor is connected between the connection nodes of the respective differential pairs and current sources. A transitional current path of the capacitor restrains voltage variations during differential input signal switching. Further in a signal detection apparatus suitable for realizing the detection of fast transmitted differential input signals with less current consumption and at low cost, an edge detect signal is supplied against a differential input of or above a prescribed value, and a setting signal is issued when this edge detect signal has been detected a prescribed number of times during a first prescribed length of time while a resetting signal is issued if none is detected during a second prescribed length of time. A signal-detect signal is generated from these setting signal and resetting signal.
摘要翻译：在差分输出信号电路中，由于输入信号的滞后而导致差分输出端子上的电压过冲/欠压，从而实现差分输入信号的稳定和快速切换，即PMOS的第一个差分对。连接到第一电流源的晶体管和连接到第二电流源的NMOS晶体管的第二差分对在差分输出端子处相互连接，并且电容器连接在各个差分对和电流源的连接节点之间。电容器的过渡电流路径抑制差分输入信号切换期间的电压变化。此外，在适于实现具有较少电流消耗和低成本的快速传输的差分输入信号的检测的信号检测装置中，针对规定值的或高于规定值的差分输入提供边缘检测信号，并且当如果在第二规定时间长度内没有检测到复位信号，则在第一规定时间长度内已经检测到该边缘检测信号规定次数。从这些设定信号和复位信号产生信号检测信号。

4. 发明申请

US20030227900A1 Portable terminal supporting apparatus, data synchronizing method, and portable terminal apparatus 审中-公开
标题翻译：便携式终端支持装置，数据同步方法和便携式终端装置
公开(公告)号：US20030227900A1
公开(公告)日：2003-12-11
申请号：US10342676
申请日：2003-01-15
申请人： FUJITSU LIMITED
发明人： Hideaki Watanabe
IPC分类号： H04J003/06
CPC分类号： G06F16/27
摘要： A PDA transmits updated data to a cradle 230. When a PC is connected to the cradle, the updated data is transferred to the PC. Similarly, the PC transmits updated data to the cradle and when the PDA is connected to the cradle, the updated data is transferred to the PDA. Thus, synchronization of data can be achieved between the PC and the PDA. Another PDA may be used instead of the PC.
摘要翻译： PDA将更新的数据发送到支架230.当PC连接到支架时，更新的数据被传送到PC。类似地，PC将更新的数据发送到支架，并且当PDA连接到支架时，更新的数据被传送到PDA。因此，可以在PC和PDA之间实现数据的同步。可以使用另一个PDA代替PC。

5. 发明申请

US20010004352A1 Data communication system, data receiving terminal and data sending terminal 失效
标题翻译：数据通信系统，数据接收终端和数据发送终端
公开(公告)号：US20010004352A1
公开(公告)日：2001-06-21
申请号：US09735887
申请日：2000-12-13
申请人： FUJITSU LIMITED
发明人： Hideaki Watanabe , Takashi Hamano
IPC分类号： H04L012/56
CPC分类号： H04L12/6418 , H04L2012/6472 , H04L2012/6475
摘要： At a data receiving terminal, if a received-data of a particular time section received from a data sending terminal does not satisfy a predetermined accumulation quality as the result of discrimination by a received-data quality discriminating section, an alternative-data sending requesting section requests a data sending terminal for alternative data satisfying the accumulation quality for the unsatisfied data of the particular time section. The result is that the data receiving terminal can realize both reproduction of data with less sending delay and accumulation of high-quality data.
摘要翻译：在数据接收终端，如果从数据发送终端接收到的特定时间段的接收数据作为接收数据质量鉴别部分的鉴别结果不满足预定的累积质量，则替换数据发送请求部分请求数据发送终端为满足特定时间段的不满足数据的累积质量的替代数据。结果是，数据接收终端可以实现具有较少发送延迟的数据的再现和高质量数据的累积。

6. 发明申请

US20040157589A1 Communication device, and method and computer program for information processing thereof 失效
标题翻译：通信装置，以及用于信息处理的方法和计算机程序
公开(公告)号：US20040157589A1
公开(公告)日：2004-08-12
申请号：US10694989
申请日：2003-10-29
申请人： Fujitsu Limited
发明人： Hideaki Watanabe , Naoyuki Inoue
IPC分类号： H04M003/42
CPC分类号： H04L29/12103 , H04L61/1535 , H04L67/16 , H04M1/274508 , H04M1/27455 , H04M1/7253 , H04M2250/02 , H04W8/22 , H04W8/26 , H04W88/02
摘要： A communication device relates a plurality of identification information to specifying information included in the identification information and manages them, and thereby enhances easiness of identifying and specifying of a device of the other party and usability of a connection with the device of the other party. The communication device has an identification information reception part (a radio transmission/reception part, a baseband part and a control part), a storage part (a data base part) and an information processing part (a control part). The identification information reception part receives the pieces of identification information concerning the device of the other party to be connected, and in the storage part the pieces of identification information which are received are stored. The information processing part stores the pieces of identification information, which are received, in the storage part, and retrieves the identification information from the storage part by receiving input of the specifying information out of the pieces of identification information, and relates a result of that retrieval to the specifying information and outputs them, or makes that output possible. By this, it is possible to use the pieces of identification information related to the specifying information for specifying of the device of the other party and connection with it.
摘要翻译：通信装置将多个识别信息与包括在识别信息中的指定信息相关联并进行管理，从而增强了对另一方的设备的识别和指定的容易性以及与另一方的设备的连接的可用性。通信设备具有识别信息接收部分（无线电发送/接收部分，基带部分和控制部分），存储部分（数据库部分）和信息处理部分（控制部分）。识别信息接收部接收与要连接的另一方的设备有关的识别信息，并且在存储部中存储接收的识别信息。信息处理部分将存储部分中接收的识别信息存储在存储部分中，并通过从识别信息中接收到指定信息的输入来从存储部分检索识别信息，并将其结果检索到指定信息并输出，或使输出成为可能。由此，可以使用与用于指定对方的设备的指定信息相关的识别信息以及与其的连接。

7. 发明申请

US20030001666A1 Differential signal output apparatus, semiconductor integrated circuit apparatus having the differential signal output apparatus, differential signal transmission system, signal detection apparatus, signal detection method, signal transmission system and computer-readable program 有权
标题翻译：差分信号输出装置，具有差分信号输出装置，差分信号传输系统，信号检测装置，信号检测方法，信号传输系统和计算机可读程序的半导体集成电路装置
公开(公告)号：US20030001666A1
公开(公告)日：2003-01-02
申请号：US09973767
申请日：2001-10-11
申请人： Fujitsu Limited
发明人： Hideaki Watanabe , Hiroko Haraguchi
IPC分类号： G06G007/12
CPC分类号： H04L25/0286 , H03F3/45237 , H03F2203/45466 , H03K5/08 , H03K5/19 , H03K5/2481 , H04L25/0272
摘要： In a differential output signal circuit suitable for restraining voltage overshooting/undershooting at differential output terminals due to lags in input signals and realizing stable and fast switching of differential input signals, a first differential pair of PMOS transistors connected to a first current source and a second differential pair of NMOS transistors connected to a second current source are mutually connected at the differential output terminals, and a capacitor is connected between the connection nodes of the respective differential pairs and current sources. A transitional current path of the capacitor restrains voltage variations during differential input signal switching. Further in a signal detection apparatus suitable for realizing the detection of fast transmitted differential input signals with less current consumption and at low cost, an edge detect signal is supplied against a differential input of or above a prescribed value, and a setting signal is issued when this edge detect signal has been detected a prescribed number of times during a first prescribed length of time while a resetting signal is issued if none is detected during a second prescribed length of time. A signal-detect signal is generated from these setting signal and resetting signal.
摘要翻译：在差分输出信号电路中，由于输入信号的滞后而在差分输出端子上抑制电压过冲/下冲并实现差分输入信号的稳定和快速切换，差分输出信号电路连接到第一电流源和第二电流源的第一差分PMOS晶体管连接到第二电流源的NMOS晶体管的差分对在差分输出端子处相互连接，并且电容器连接在各个差分对和电流源的连接节点之间。电容器的过渡电流路径抑制差分输入信号切换期间的电压变化。此外，在适于实现具有较少电流消耗和低成本的快速传输的差分输入信号的检测的信号检测装置中，针对规定值的或高于规定值的差分输入提供边缘检测信号，并且当如果在第二规定时间长度内没有检测到复位信号，则在第一规定时间长度内已经检测到该边缘检测信号规定次数。从这些设定信号和复位信号产生信号检测信号。

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