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1. 发明授权

US08441127B2 Bump-on-trace structures with wide and narrow portions 有权
标题翻译：具有宽和窄部分的凸起跟踪结构
公开(公告)号：US08441127B2
公开(公告)日：2013-05-14
申请号：US13172470
申请日：2011-06-29
申请人： Fu-Tsai Hou , Liang-Chen Lin
发明人： Fu-Tsai Hou , Liang-Chen Lin
IPC分类号： H01L23/498
CPC分类号： H01L23/49811 , H01L23/49822 , H01L24/13 , H01L24/16 , H01L24/81 , H01L2224/0401 , H01L2224/05572 , H01L2224/13014 , H01L2224/13082 , H01L2224/16237 , H01L2924/00011 , H01L2924/00014 , H01L2924/01322 , H01L2924/00012 , H01L2924/00 , H01L2224/05552 , H01L2224/81805
摘要： A device includes a package component, and a metal trace on a surface of the package component. A first and a second dielectric mask cover a top surface and sidewalls of the metal trace, wherein a landing portion of the metal trace is located between the first and the second dielectric masks. The landing portion includes a first portion having a first width, and a second portion connected to an end of the first portion. The second portion has a second width greater than the first width, wherein the first and the second widths are measured in a direction perpendicular to a lengthwise direction of the metal trace.
摘要翻译：一种装置包括封装部件和在封装部件的表面上的金属迹线。第一和第二介电掩模覆盖金属迹线的顶表面和侧壁，其中金属迹线的着陆部分位于第一和第二介电掩模之间。着陆部分包括具有第一宽度的第一部分和连接到第一部分的端部的第二部分。第二部分具有大于第一宽度的第二宽度，其中在垂直于金属迹线的长度方向的方向上测量第一宽度和第二宽度。

2. 发明申请

US20130001769A1 Bump-on-Trace Structures with Increased Current Entrance Areas 有权
标题翻译：具有增加的当前入口区域的凸起跟踪结构
公开(公告)号：US20130001769A1
公开(公告)日：2013-01-03
申请号：US13172470
申请日：2011-06-29
申请人： Fu-Tsai Hou , Liang-Chen Lin
发明人： Fu-Tsai Hou , Liang-Chen Lin
IPC分类号： H01L23/498
CPC分类号： H01L23/49811 , H01L23/49822 , H01L24/13 , H01L24/16 , H01L24/81 , H01L2224/0401 , H01L2224/05572 , H01L2224/13014 , H01L2224/13082 , H01L2224/16237 , H01L2924/00011 , H01L2924/00014 , H01L2924/01322 , H01L2924/00012 , H01L2924/00 , H01L2224/05552 , H01L2224/81805
摘要： A device includes a package component, and a metal trace on a surface of the package component. A first and a second dielectric mask cover a top surface and sidewalls of the metal trace, wherein a landing portion of the metal trace is located between the first and the second dielectric masks. The landing portion includes a first portion having a first width, and a second portion connected to an end of the first portion. The second portion has a second width greater than the first width, wherein the first and the second widths are measured in a direction perpendicular to a lengthwise direction of the metal trace.
摘要翻译：一种装置包括封装部件和在封装部件的表面上的金属迹线。第一和第二介电掩模覆盖金属迹线的顶表面和侧壁，其中金属迹线的着陆部分位于第一和第二介电掩模之间。着陆部分包括具有第一宽度的第一部分和连接到第一部分的端部的第二部分。第二部分具有大于第一宽度的第二宽度，其中在垂直于金属迹线的长度方向的方向上测量第一宽度和第二宽度。

3. 发明申请

US20090121222A1 Test Structure 有权
标题翻译：测试结构
公开(公告)号：US20090121222A1
公开(公告)日：2009-05-14
申请号：US12354338
申请日：2009-01-15
申请人： Ta-Chih Peng , Yu-Ting Lin , Liang-Chen Lin , Ko-Yi Lee
发明人： Ta-Chih Peng , Yu-Ting Lin , Liang-Chen Lin , Ko-Yi Lee
IPC分类号： H01L23/488
CPC分类号： H01L24/05 , H01L22/34 , H01L2224/05093 , H01L2224/05096 , H01L2224/05556 , H01L2224/05624 , H01L2224/05647 , H01L2924/01013 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/014 , H01L2924/14 , H01L2924/00014 , H01L2924/00
摘要： A test structure to detect vertical leakage in a multi-layer flip chip pad stack or similar semiconductor device. The test structure is integrated into the semiconductor device when it is fabricated. A metal layer includes at least two portions that are electrically isolated from each other; one portion being disposed under a test pad, and another portion being disposed under a pad associated with a pad structure being tested. The metal layer in most cases is separated from a top metal layer directly underlying the pads by an inter-metal dielectric (IMD) layer. A metal layer portion underlying the pad to be tested forms a recess in which a conductive member is disposed without making electrical contact. The conductive line is electrically coupled to a test portion of the same or, alternately, of a different metal layer. The test structure may be implemented on multiple layers, with recesses portions underlying the same or different pads.
摘要翻译：用于检测多层倒装芯片堆栈或类似半导体器件中的垂直泄漏的测试结构。测试结构在制造时被集成到半导体器件中。金属层包括彼此电隔离的至少两个部分; 一部分设置在测试垫下方，另一部分设置在与被测试的垫结构相关联的垫下方。大多数情况下，金属层通过金属间电介质（IMD）层与直接位于焊盘下方的顶部金属层分离。待测试垫下面的金属层部分形成凹部，其中布置导电部件而不进行电接触。导电线电耦合到相同或交替地不同金属层的测试部分。测试结构可以在多个层上实现，其中凹陷部分位于相同或不同的垫下。

4. 发明申请

US20080083992A1 NOVEL BONDING AND PROBING PAD STRUCTURES 有权
标题翻译：新型结合和探测垫结构
公开(公告)号：US20080083992A1
公开(公告)日：2008-04-10
申请号：US11539498
申请日：2006-10-06
申请人： Liang-Chen Lin , Pei-Haw Tsao
发明人： Liang-Chen Lin , Pei-Haw Tsao
IPC分类号： H01L21/44 , H01L23/485
CPC分类号： H01L24/05 , H01L24/03 , H01L24/45 , H01L24/48 , H01L2224/02166 , H01L2224/04042 , H01L2224/05006 , H01L2224/05093 , H01L2224/05096 , H01L2224/05567 , H01L2224/05572 , H01L2224/05647 , H01L2224/45124 , H01L2224/48463 , H01L2224/48747 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01007 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01073 , H01L2924/01078 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/12041 , H01L2924/14 , H01L2924/00014 , H01L2924/00 , H01L2224/05552
摘要： A pad structure includes a first metal-containing layer formed over a substrate. A first passivation layer is formed over the first metal-containing layer. The first passivation layer has a first opening partially exposing the first metal-containing layer. A pad layer is formed over the first passivation layer, covering the first opening. The pad layer includes a probing region configured to be contacted by a probe and a bonding region configured to have a wired bonded to it. The probing region contacts the first metal-containing layer through the first opening, and the bonding region overlies a portion of the first passivation layer.
摘要翻译：衬垫结构包括在衬底上形成的第一含金属层。在第一含金属层上形成第一钝化层。第一钝化层具有部分暴露第一含金属层的第一开口。衬垫层形成在第一钝化层上，覆盖第一开口。衬垫层包括构造成由探针接触的探测区域和被配置为与其接合的接合区域。探测区域通过第一开口接触第一含金属层，并且接合区域覆盖第一钝化层的一部分。

5. 发明授权

US09508617B2 Test chip, test board and reliability testing method 有权
标题翻译：测试芯片，测试板和可靠性测试方法
公开(公告)号：US09508617B2
公开(公告)日：2016-11-29
申请号：US13411193
申请日：2012-03-02
申请人： Shiang-Ruei Su , Liang-Chen Lin , Chia-Wei Tu
发明人： Shiang-Ruei Su , Liang-Chen Lin , Chia-Wei Tu
IPC分类号： H01L21/66 , G01R31/28
CPC分类号： G01R31/2856 , H01L21/4853 , H01L22/14 , H01L22/34 , H01L24/16 , H01L2224/16157 , H01L2924/0002 , H01L2924/00
摘要： A test board includes a first chip mounting area, a first input area, a second input area, a first output area, and a second output area. The test board also includes a first conductive pattern, a second conductive pattern, a third conductive pattern, and a fourth conductive pattern. The first conductive pattern electrically connects a first pin of the first input area and a first pin of the first chip mounting area. The second conductive pattern electrically connects a first pin of the second input area and a second pin of the first chip mounting area. The third conductive pattern electrically connects a first pin of the first output area and a third pin of the first chip mounting area. The fourth conductive pattern electrically connects a first pin of the second output area and a fourth pin of the first chip mounting area.
摘要翻译：测试板包括第一芯片安装区域，第一输入区域，第二输入区域，第一输出区域和第二输出区域。测试板还包括第一导电图案，第二导电图案，第三导电图案和第四导电图案。第一导电图形电连接第一输入区域的第一引脚和第一芯片安装区域的第一引脚。第二导电图形电连接第二输入区域的第一引脚和第一芯片安装区域的第二引脚。第三导电图形电连接第一输出区域的第一引脚和第一芯片安装区域的第三引脚。第四导电图形电连接第二输出区域的第一引脚和第一芯片安装区域的第四引脚。

6. 发明授权

US07939824B2 Test structure 有权
标题翻译：测试结构
公开(公告)号：US07939824B2
公开(公告)日：2011-05-10
申请号：US12354338
申请日：2009-01-15
申请人： Ta-Chih Peng , Yu-Ting Lin , Liang-Chen Lin , Ko-Yi Lee
发明人： Ta-Chih Peng , Yu-Ting Lin , Liang-Chen Lin , Ko-Yi Lee
IPC分类号： H01L23/58 , H01L29/10
CPC分类号： H01L24/05 , H01L22/34 , H01L2224/05093 , H01L2224/05096 , H01L2224/05556 , H01L2224/05624 , H01L2224/05647 , H01L2924/01013 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/014 , H01L2924/14 , H01L2924/00014 , H01L2924/00
摘要： A test structure to detect vertical leakage in a multi-layer flip chip pad stack or similar semiconductor device. The test structure is integrated into the semiconductor device when it is fabricated. A metal layer includes at least two portions that are electrically isolated from each other; one portion being disposed under a test pad, and another portion being disposed under a pad associated with a pad structure being tested. The metal layer in most cases is separated from a top metal layer directly underlying the pads by an inter-metal dielectric (IMD) layer. A metal layer portion underlying the pad to be tested forms a recess in which a conductive member is disposed without making electrical contact. The conductive line is electrically coupled to a test portion of the same or, alternately, of a different metal layer. The test structure may be implemented on multiple layers, with recesses portions underlying the same or different pads.
摘要翻译：用于检测多层倒装芯片堆栈或类似半导体器件中的垂直泄漏的测试结构。测试结构在制造时被集成到半导体器件中。金属层包括彼此电隔离的至少两个部分; 一部分设置在测试垫下方，另一部分设置在与被测试的垫结构相关联的垫下方。大多数情况下，金属层通过金属间电介质（IMD）层与直接位于焊盘下方的顶部金属层分离。待测试垫下面的金属层部分形成凹部，其中布置导电部件而不进行电接触。导电线电耦合到相同或交替地不同金属层的测试部分。测试结构可以在多个层上实现，其中凹陷部分位于相同或不同的垫下。

7. 发明申请

US20080122100A1 NOVEL BOND PAD DESIGN TO MINIMIZE DIELECTRIC CRACKING 有权
标题翻译：新型贴膜设计，以最小化电介质破碎
公开(公告)号：US20080122100A1
公开(公告)日：2008-05-29
申请号：US11557372
申请日：2006-11-07
申请人： Pei-Haw Tsao , Liang-Chen Lin , Pao-Kang Niu , I-Tai Liu , Bill Kiang
发明人： Pei-Haw Tsao , Liang-Chen Lin , Pao-Kang Niu , I-Tai Liu , Bill Kiang
IPC分类号： H01L23/488 , H01L21/4763
CPC分类号： H01L24/05 , H01L24/03 , H01L2224/02166 , H01L2224/05093 , H01L2224/05094 , H01L2224/05554 , H01L2224/05556 , H01L2224/056 , H01L2924/00014 , H01L2924/01005 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01082 , H01L2924/14
摘要： An improved via arrangement for a bonding pad structure is disclosed comprising an array of vias surrounded by a line via. The line via provides a barrier to cracks in the dielectric layer encompassing the via array. Although cracks are able to spread relatively unhindered between the vias of the via array, they are blocked by the line via and thus can not spread to neighboring regions of the chip or wafer. The line via can be provided in a variety of shapes and dimensions, to suit a desired application. Additionally, due to its substantially uninterrupted length, the line via provides added strength to the bond pad.
摘要翻译：公开了一种用于焊盘结构的改进的通孔布置，其包括由线路通孔包围的通孔阵列。线路通孔提供对包围通孔阵列的介电层中的裂纹的屏障。虽然裂纹能够在通孔阵列的通孔之间相对不受阻碍地扩散，但是它们被线通孔阻挡，因此不能扩散到芯片或晶片的相邻区域。线路通孔可以以各种形状和尺寸提供，以适应期望的应用。另外，由于其基本上不间断的长度，线路通孔为接合焊盘提供附加的强度。

8. 发明申请

US20080122086A1 Solder bump structure and method of manufacturing same 有权
标题翻译：焊接凸块结构及其制造方法
公开(公告)号：US20080122086A1
公开(公告)日：2008-05-29
申请号：US11592220
申请日：2006-11-03
申请人： Pei-Haw Tsao , Bill Kiang , Pao-Kang Niu , Liang-Chen Lin , I-Tai Liu
发明人： Pei-Haw Tsao , Bill Kiang , Pao-Kang Niu , Liang-Chen Lin , I-Tai Liu
IPC分类号： H01L23/488 , H01L21/44
CPC分类号： H01L24/10 , H01L23/3192 , H01L24/13 , H01L2224/0401 , H01L2224/05124 , H01L2224/05147 , H01L2224/05572 , H01L2224/13 , H01L2224/13099 , H01L2224/16 , H01L2924/0002 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01075 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/00014 , H01L2224/05552 , H01L2924/00
摘要： Solder bump structures for semiconductor device packaging is provided. In one embodiment, a semiconductor device comprises a substrate having a bond pad and a first passivation layer formed thereabove, the first passivation layer having an opening therein exposing a portion of the bond pad. A metal pad layer is formed on a portion of the bond pad, wherein the metal pad layer contacts the bond pad. A second passivation layer is formed above the metal pad layer, the second passivation layer having an opening therein exposing a portion of the metal pad layer. A patterned and etched polyimide layer is formed on a portion of the metal pad layer and a portion of the second passivation layer. A conductive layer is formed above a portion of the etched polyimide layer and a portion of the metal pad layer, wherein the conductive layer contacts the metal pad layer. A conductive bump structure is connected to the conductive layer.
摘要翻译：提供了用于半导体器件封装的焊接凸块结构。在一个实施例中，半导体器件包括具有接合焊盘和在其上形成的第一钝化层的衬底，其中第一钝化层具有暴露焊接焊盘的一部分的开口。在接合焊盘的一部分上形成金属焊盘层，其中金属焊盘层与接合焊盘接触。第二钝化层形成在金属焊盘层的上方，第二钝化层在其中具有露出金属焊盘层的一部分的开口。图案化和蚀刻的聚酰亚胺层形成在金属焊盘层的一部分和第二钝化层的一部分上。在蚀刻的聚酰亚胺层的一部分和金属焊盘层的一部分上形成导电层，其中导电层与金属焊盘层接触。导电凸块结构连接到导电层。

9. 发明授权

US07843058B2 Flip chip packages with spacers separating heat sinks and substrates 有权
标题翻译：倒装芯片封装，分隔散热片和基板
公开(公告)号：US07843058B2
公开(公告)日：2010-11-30
申请号：US11928971
申请日：2007-10-30
申请人： Pei-Haw Tsao , Liang-Chen Lin , Pao-Kang Niu
发明人： Pei-Haw Tsao , Liang-Chen Lin , Pao-Kang Niu
IPC分类号： H01L23/34
CPC分类号： H01L23/4006 , H01L23/42 , H01L23/433 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2224/73253 , H01L2924/01004 , H01L2924/01019 , H01L2924/15311 , H01L2924/16195 , H01L2924/00012 , H01L2924/00
摘要： A package structure includes a substrate; a die over and flip bonded on the substrate; a heat sink over the die; and one or more spacer separating the heat sink from the substrate.
摘要翻译：封装结构包括基板; 在基板上切割并翻转接合; 模具上的散热片; 以及将散热器与衬底分隔开的一个或多个间隔件。

10. 发明授权

US07498680B2 Test structure 有权
标题翻译：测试结构
公开(公告)号：US07498680B2
公开(公告)日：2009-03-03
申请号：US11634588
申请日：2006-12-06
申请人： Ta-Chih Peng , Yu-ting Lin , Liang-Chen Lin , Ko-Yi Lee
发明人： Ta-Chih Peng , Yu-ting Lin , Liang-Chen Lin , Ko-Yi Lee
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L24/05 , H01L22/34 , H01L2224/05093 , H01L2224/05096 , H01L2224/05556 , H01L2224/05624 , H01L2224/05647 , H01L2924/01013 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/014 , H01L2924/14 , H01L2924/00014 , H01L2924/00
摘要： A test structure to detect vertical leakage in a multi-layer flip chip pad stack or similar semiconductor device. The test structure is integrated into the semiconductor device when it is fabricated. A metal layer includes at least two portions that are electrically isolated from each other; one portion being disposed under a test pad, and another portion being disposed under a pad associated with a pad structure being tested. The metal layer in most cases is separated from a top metal layer directly underlying the pads by an inter-metal dielectric (IMD) layer. A metal layer portion underlying the pad to be tested forms a recess in which a conductive member is disposed without making electrical contact. The conductive line is electrically coupled to a test portion of the same or, alternately, of a different metal layer. The test structure may be implemented on multiple layers, with recesses portions underlying the same or different pads.
摘要翻译：用于检测多层倒装芯片堆栈或类似半导体器件中的垂直泄漏的测试结构。测试结构在制造时被集成到半导体器件中。金属层包括彼此电隔离的至少两个部分; 一部分设置在测试垫下方，另一部分设置在与待测试的垫结构相关联的垫下方。大多数情况下，金属层通过金属间电介质（IMD）层与直接位于焊盘下方的顶部金属层分离。待测试垫下面的金属层部分形成凹部，其中布置导电部件而不进行电接触。导电线电耦合到相同或交替地不同金属层的测试部分。测试结构可以在多层上实现，其中凹部位于相同或不同的垫下。

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