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1. 发明授权

US08347487B2 Fabricating method of magnetoresistance sensor 有权
标题翻译：磁阻传感器的制造方法
公开(公告)号：US08347487B2
公开(公告)日：2013-01-08
申请号：US13174758
申请日：2011-06-30
申请人： Fu-Tai Liou , Chih-Chien Liang , Chien-Min Lee
发明人： Fu-Tai Liou , Chih-Chien Liang , Chien-Min Lee
IPC分类号： G11B5/127 , H04R31/00
CPC分类号： G01R33/093 , B82Y25/00 , G01R33/098 , H01L43/02 , H01L43/08 , H01L43/12 , Y10T29/49032 , Y10T29/49041 , Y10T29/49043 , Y10T29/49044 , Y10T29/49046 , Y10T29/49048 , Y10T29/49052 , Y10T428/12465 , Y10T428/12632 , Y10T428/12903
摘要： A fabricating method of a magnetoresistance sensor is provided with cost effective and process flexibility features. Firstly, a substrate is provided. Then, at least one magnetoresistance structure and at least one bonding pad are formed over the substrate, wherein the bonding pad is electrically connected with the magnetoresistance structure. Then, a passivation layer is formed over the magnetoresistance structure and the bonding pad. Then, a magnetic shielding and concentrator structure is formed over the passivation layer at a location corresponding to the magnetoresistance structure. Finally, bonding pad openings is formed on the passivation layer by patterned polyimide, thereby exposing the bonding pad. After bonding pad was opened, the patterned polyimide can be removed or retained as an additional protection layer.
摘要翻译：磁阻传感器的制造方法具有成本效益和工艺灵活性。首先，提供基板。然后，在衬底上形成至少一个磁阻结构和至少一个焊盘，其中焊盘与磁阻结构电连接。然后，在磁阻结构和接合焊盘上形成钝化层。然后，在对应于磁阻结构的位置处，在钝化层上形成磁屏蔽和集中器结构。最后，通过图案化的聚酰亚胺在钝化层上形成焊盘开口，从而露出焊盘。在打开焊盘后，图案化的聚酰亚胺可以作为附加保护层被去除或保留。

2. 发明授权

US08871529B2 Method for manufacturing integrated circuit structure with magnetoresistance component 有权
标题翻译：用于制造具有磁阻部件的集成电路结构的方法
公开(公告)号：US08871529B2
公开(公告)日：2014-10-28
申请号：US13427875
申请日：2012-03-22
申请人： Fu-Tai Liou , Chien-Min Lee , Chih-Chien Liang , Nai-Chung Fu
发明人： Fu-Tai Liou , Chien-Min Lee , Chih-Chien Liang , Nai-Chung Fu
IPC分类号： H01L21/00 , H01L43/12
CPC分类号： H01L43/12
摘要： A method or manufacturing an integrated circuit structure with a magnetoresistance component is provided. A substrate is provided. A circuit structure layer including a metal pad is formed on the substrate. A dielectric layer is formed on the circuit structure. A metal damascene structure is formed in the dielectric layer. An opening is formed in the dielectric layer so as to form a step-drop. A magnetoresistance material layer is formed on the dielectric layer after forming the metal damascene structure and the opening. A photolithography process is applied to pattern the magnetoresistance material layer to form a magnetoresistance component electrically connected to the metal damascene structure.
摘要翻译：提供了一种制造具有磁阻部件的集成电路结构的方法或制造方法。提供基板。在基板上形成包括金属焊盘的电路结构层。在电路结构上形成介电层。在电介质层中形成金属镶嵌结构。在电介质层中形成开口以便形成分步骤。在形成金属镶嵌结构和开口之后，在电介质层上形成磁阻材料层。应用光刻工艺以对磁阻材料层进行图案化以形成电连接到金属镶嵌结构的磁阻组件。

3. 发明授权

US09030199B2 Magnetoresistance sensor and fabricating method thereof 有权
标题翻译：磁阻传感器及其制造方法
公开(公告)号：US09030199B2
公开(公告)日：2015-05-12
申请号：US13082825
申请日：2011-04-08
申请人： Fu-Tai Liou , Chien-Min Lee
发明人： Fu-Tai Liou , Chien-Min Lee
IPC分类号： G01R33/02 , H05K3/42 , H05K3/46 , G01R33/09 , B82Y25/00 , G01D5/16 , G01R33/06
CPC分类号： G01R33/093 , B82Y25/00 , G01D5/16 , G01R33/06 , G01R33/09 , Y10T29/49155 , Y10T29/49165
摘要： An apparatus of a magnetoresistance sensor consisting of a substrate, a conductive unit on the substrate, and a magnetoresistance structure on the conductive unit is provided. The conductive unit includes a first surface and a second surface opposite to each other, and the first surface faces the substrate. The magnetoresistance structure is formed on the second surface of the conductive unit and is electrically connected to the conductive unit. The magnetoresistance sensor has high performance and reliability. A magnetoresistance sensor fabricating method based on this apparatus is also provided.
摘要翻译：提供了由基板，基板上的导电单元和导电单元上的磁阻结构构成的磁阻传感器的装置。导电单元包括彼此相对的第一表面和第二表面，并且第一表面面向基板。磁阻结构形成在导电单元的第二表面上并与导电单元电连接。磁阻传感器具有高性能和可靠性。还提供了一种基于该装置的磁阻传感器制造方法。

4. 发明授权

US08629519B2 Tunneling magnetoresistance sensor 失效
标题翻译：隧道磁阻传感器
公开(公告)号：US08629519B2
公开(公告)日：2014-01-14
申请号：US13333951
申请日：2011-12-21
申请人： Chien-Min Lee , Kuang-Ching Chen , Fu-Tai Liou
发明人： Chien-Min Lee , Kuang-Ching Chen , Fu-Tai Liou
IPC分类号： H01L29/82
CPC分类号： H01L43/02 , G01R33/098 , H01F10/3254 , H01L27/22
摘要： A tunneling magnetoresistance sensor including a substrate, an insulating layer, a tunneling magnetoresistance component and an electrode array is provided. The insulating layer is disposed on the substrate. The tunneling magnetoresistance component is embedded in the insulating layer. The electrode array is formed in a single metal layer and disposed in the insulating layer either below or above the TMR component. The electrode array includes a number of separate electrodes. The electrodes are electrically connected to the tunneling magnetoresistance component to form a current-in-plane tunneling conduction mode. The tunneling magnetoresistance sensor in this configuration can be manufactured with a reduced cost and maintain the high performance at the same time.
摘要翻译：提供了包括基板，绝缘层，隧道磁阻部件和电极阵列的隧道式磁阻传感器。绝缘层设置在基板上。隧道磁阻分量嵌入在绝缘层中。电极阵列形成在单个金属层中，并且设置在TMR部件的下方或上方的绝缘层中。电极阵列包括多个单独的电极。电极电连接到隧道磁阻分量以形成电流 - 平面隧穿传导模式。这种结构中的隧道磁阻传感器可以以降低的成本制造并且同时保持高性能。

5. 发明授权

US07067917B2 Gradient barrier layer for copper back-end-of-line technology 有权
标题翻译：用于铜后端技术的梯度屏障层
公开(公告)号：US07067917B2
公开(公告)日：2006-06-27
申请号：US10337292
申请日：2003-01-07
申请人： Fu-Tai Liou , Cheng-Yu Hung , Tri-Rung Yew
发明人： Fu-Tai Liou , Cheng-Yu Hung , Tri-Rung Yew
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/76846 , C23C14/027 , C23C14/0641 , C23C16/029 , C23C16/34 , H01L21/2855 , H01L21/28556 , H01L21/76805 , H01L21/76864 , H01L23/53238 , H01L2924/0002 , Y10T428/26 , H01L2924/00
摘要： The present invention is directed to a structure of a gradient barrier layer. The gradient barrier with a composite structure of metal/metal salt of different composition/metal such as Ta/TaxN1−x/TaN/TaxN1−x/Ta (tantalum/tantalumx nitride1−x/tantalum nitride/tantalumx nitride1−x/tantalum) is proposed to replace the conventional barrier for copper metallization. The gradient barrier can be formed in a chemical vapor deposition (CVD) process or a multi-target physical vapor deposition (PVD) process. For CVD process, using the characteristics of well-controlled reaction gas injection, the ratio of tantalum (Ta) and nitrogen (N) can be modulated gradually to form the gradient barrier. For the multi-target PVD process, the gradient barrier is formed by depositing multi-layers of different composition TaxN1−x films. After subsequent thermal cycle processes such as metal alloy, the inter-layer diffusion occurs and a more smooth distribution of Ta and N is achieved for the gradient barrier. The advantages of forming the gradient barrier include a well-controlled process, a strong adhesion between via and landing metal, more uniform step coverage, and less brittle to reduce crack.
摘要翻译：本发明涉及梯度阻挡层的结构。具有不同成分/金属的金属/金属盐的复合结构的梯度屏障，例如Ta / Ta x N 1-x / TaN / Ta x x 1 / x 1 / x 3/1 / x 2/1 / x 3 / 提出了替代传统的铜金属化屏障的方法。梯度屏障可以在化学气相沉积（CVD）工艺或多目标物理气相沉积（PVD）工艺中形成。对于CVD工艺，使用良好控制的反应气体注入特性，可以逐渐调节钽（Ta）和氮（N）的比例，形成梯度屏障。对于多目标PVD工艺，通过沉积多层不同组成的Ta x N 1 x-x膜形成梯度屏障。在随后的热循环过程如金属合金之后，发生层间扩散，并且对梯度屏障实现了更平稳的Ta和N分布。形成梯度屏障的优点包括良好控制的工艺，通孔和着陆金属之间的牢固粘附，更均匀的台阶覆盖，并且较不易碎以减少裂纹。

6. 发明授权

US06287963B1 Method for forming a metal contact 失效
标题翻译：形成金属接触的方法
公开(公告)号：US06287963B1
公开(公告)日：2001-09-11
申请号：US08418257
申请日：1995-04-06
申请人： Fusen E. Chen , Fu-Tai Liou , Girish A. Dixit , Che-Chia Wei
发明人： Fusen E. Chen , Fu-Tai Liou , Girish A. Dixit , Che-Chia Wei
IPC分类号： H01L214763
CPC分类号： H01L23/53223 , C23C16/0281 , C23C16/20 , H01L21/28512 , H01L21/32051 , H01L21/7684 , H01L21/76877 , H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： A method is provided for depositing aluminum thin film layers to form contacts in a semiconductor integrated circuit device. All or some of the deposition process occurs at relatively low deposition rates at a temperature which allows surface migration of the deposited aluminum atoms. Aluminum deposited under these conditions tends to fill contact vias without the formation of voids. The deposition step is periodically interrupted.
摘要翻译：提供了一种用于在半导体集成电路器件中沉积铝薄膜层以形成接触的方法。所有或一些沉积过程在允许沉积的铝原子的表面迁移的温度下以相对低的沉积速率发生。在这些条件下沉积的铝倾向于填充接触孔而不形成空隙。沉积步骤被周期性地中断。

7. 发明授权

US06271137B1 Method of producing an aluminum stacked contact/via for multilayer 失效
标题翻译：生产用于多层的铝叠层接触/通孔的方法
公开(公告)号：US06271137B1
公开(公告)日：2001-08-07
申请号：US08146823
申请日：1993-11-01
申请人： Fu-Tai Liou , Fusen E. Chen
发明人： Fu-Tai Liou , Fusen E. Chen
IPC分类号： H01L2144
CPC分类号： H01L23/53223 , C23C16/0281 , C23C16/20 , H01L21/28512 , H01L21/32051 , H01L21/76843 , H01L21/76877 , H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： A method is provided for forming improved quality interlevel aluminum contacts in semiconductor integrated circuits. A contact opening is formed through an insulating layer. A barrier layer is deposited over the surface of the integrated circuit. An aluminum layer is then deposited at relatively low deposition rates at a temperature which allows improved surface migration of the deposited aluminum atoms. Aluminum deposited under these conditions tends to fill contact vias without the formation of voids. The low temperature deposition step can be initiated by depositing aluminum while a wafer containing the integrated circuit device is being heated from cooler temperatures within the deposition chamber.
摘要翻译：提供了一种用于在半导体集成电路中形成改进的质量层间铝触点的方法。通过绝缘层形成接触开口。势垒层沉积在集成电路的表面上。然后在允许改善沉积的铝原子的表面迁移的温度下以相对低的沉积速率沉积铝层。在这些条件下沉积的铝倾向于填充接触孔而不形成空隙。低温沉积步骤可以通过沉积铝来开始，而包含集成电路器件的晶片正在从沉积室内的较冷的温度加热。

8. 发明授权

US6111319A Method of forming submicron contacts and vias in an integrated circuit 失效
标题翻译：在集成电路中形成亚微米触点和通孔的方法
公开(公告)号：US6111319A
公开(公告)日：2000-08-29
申请号：US575691
申请日：1995-12-19
申请人： Fu-Tai Liou , Mehdi Zamanian
发明人： Fu-Tai Liou , Mehdi Zamanian
IPC分类号： H01L21/302 , H01L21/3065 , H01L21/768 , H01L23/522 , H01L23/48
CPC分类号： H01L21/76831 , H01L21/76802 , H01L21/76807
摘要： A method is provided of forming a small geometry via or contact of a semiconductor integrated circuit, and an integrated circuit formed according to the same, is disclosed. According to a first disclosed embodiment, an opening is formed partially through an insulating layer overlying a conductive region. Sidewall spacers are formed along the sidewalls of the opening. The remaining insulating layer is etched to expose the underlying conductive region. The contact dimension of the opening is smaller than the opening which can be printed from modern photolithography techniques. According to an alternate embodiment, the opening in the insulating layer expose the underlying conductive region. A polysilicon layer is formed over the insulating layer and in the opening. The polysilicon is oxidized to form a thick oxide in the opening and is etched back to form oxidized polysilicon sidewall spacers which decrease the contact dimension of the opening. According to a further alternate embodiment, an etch stop layer is formed between the insulating layer and conductive region and an opening is formed in the insulating layer exposing the etch stop layer. A sidewall spacer film is formed over the insulating layer and the etch stop layer, both layers having a similar etch rate for a given etchant. The etch stop and spacer layers are etched in the opening to expose the underlying conductive layer thereby forming a contiguous sidewall spacer and etch stop layer on the sides of and under the insulating layer, thereby decreasing the contact dimension of the opening.
摘要翻译：公开了一种通过半导体集成电路或接触形成小几何形状的方法，以及根据该半导体集成电路形成的集成电路。根据第一公开的实施例，部分地通过覆盖导电区域的绝缘层形成开口。沿着开口的侧壁形成侧壁间隔物。蚀刻剩余的绝缘层以暴露下面的导电区域。开口的接触尺寸小于可以用现代光刻技术印刷的开口。根据替代实施例，绝缘层中的开口暴露下面的导电区域。在绝缘层和开口中形成多晶硅层。多晶硅被氧化以在开口中形成厚的氧化物并被回蚀以形成减小开口的接触尺寸的氧化的多晶硅侧壁间隔物。根据另一替代实施例，在绝缘层和导电区域之间形成蚀刻停止层，并且在暴露蚀刻停止层的绝缘层中形成开口。在绝缘层和蚀刻停止层上形成侧壁间隔膜，两层对于给定的蚀刻剂具有相似的蚀刻速率。蚀刻停止层和间隔层在开口中被蚀刻以暴露下面的导电层，从而在绝缘层上和下方形成连续的侧壁间隔物和蚀刻停止层，从而减小开口的接触尺寸。

9. 发明授权

US5847460A Submicron contacts and vias in an integrated circuit 失效
标题翻译：亚微米触点和通孔在集成电路中
公开(公告)号：US5847460A
公开(公告)日：1998-12-08
申请号：US574659
申请日：1995-12-19
申请人： Fu-Tai Liou , Mehdi Zamanian
发明人： Fu-Tai Liou , Mehdi Zamanian
IPC分类号： H01L21/302 , H01L21/3065 , H01L21/768 , H01L23/522 , H01L23/48 , H01L23/52 , H01L23/58 , H01L29/40
CPC分类号： H01L21/76831 , H01L21/76807
摘要： A method is provided of forming a small geometry via or contact of a semiconductor integrated circuit, and an integrated circuit formed according to the same, is disclosed. According to a first disclosed embodiment, an opening is formed partially through an insulating layer overlying a conductive region. Sidewall spacers are formed along the sidewalls of the opening. The remaining insulating layer is etched to expose the underlying conductive region. The contact dimension of the opening is smaller than the opening which can be printed from modern photolithography techniques. According to an alternate embodiment, the opening in the insulating layer expose the underlying conductive region. A polysilicon layer is formed over the insulating layer and in the opening. The polysilicon is oxidized to form a thick oxide in the opening and is etched back to form oxidized polysilicon sidewall spacers which decrease the contact dimension of the opening. According to a further alternate embodiment, an etch stop layer is formed between the insulating layer and conductive region and an opening is formed in the insulating layer exposing the etch stop layer. A sidewall spacer film is formed over the insulating layer and the etch stop layer, both layers having a similar etch rate for a given etchant. The etch stop and spacer layers are etched in the opening to expose the underlying conductive layer thereby forming a contiguous sidewall spacer and etch stop layer on the sides of and under the insulating layer, thereby decreasing the contact dimension of the opening.
摘要翻译：公开了一种通过半导体集成电路或接触形成小几何形状的方法，以及根据该半导体集成电路形成的集成电路。根据第一公开的实施例，部分地通过覆盖导电区域的绝缘层形成开口。沿着开口的侧壁形成侧壁间隔物。蚀刻剩余的绝缘层以暴露下面的导电区域。开口的接触尺寸小于可以用现代光刻技术印刷的开口。根据替代实施例，绝缘层中的开口暴露下面的导电区域。在绝缘层和开口中形成多晶硅层。多晶硅被氧化以在开口中形成厚的氧化物并被回蚀以形成减小开口的接触尺寸的氧化的多晶硅侧壁间隔物。根据另一替代实施例，在绝缘层和导电区域之间形成蚀刻停止层，并且在暴露蚀刻停止层的绝缘层中形成开口。在绝缘层和蚀刻停止层上形成侧壁间隔膜，两层对于给定的蚀刻剂具有相似的蚀刻速率。蚀刻停止层和间隔层在开口中被蚀刻以暴露下面的导电层，从而在绝缘层上和下方形成连续的侧壁间隔物和蚀刻停止层，从而减小开口的接触尺寸。

10. 发明授权

US5462894A Method for fabricating a polycrystalline silicon resistive load element in an integrated circuit 失效
标题翻译：在集成电路中制造多晶硅电阻性负载元件的方法
公开(公告)号：US5462894A
公开(公告)日：1995-10-31
申请号：US310925
申请日：1994-09-22
申请人： Charles R. Spinner , Fu-Tai Liou
发明人： Charles R. Spinner , Fu-Tai Liou
IPC分类号： H01L21/02 , H01L27/11 , H01L29/8605
CPC分类号： H01L28/20 , H01L27/1112 , Y10S148/136 , Y10S257/904
摘要： A method for forming integrated circuit structures includes the formation of high-value resistive elements and low resistance interconnect in a single polycrystalline layer. In one embodiment, interconnect regions of the polycrystalline silicon layer are masked, and resistive element regions are partially oxidized to reduce the thickness of the polycrystalline layer in such regions. Resistivity of the interconnect regions may then be reduced by implanting a high level of impurities in them, or by forming a refractory metal silicide layer over the interconnect regions. The oxide formed over the resistive elements during the oxidation thereof protects them from either of the following process steps, so that no masking is required. In an alternative embodiment, silicidation of the interconnect regions of the polycrystalline silicon layer may be performed without the prior local oxidations of the resistive element regions.
摘要翻译：一种用于形成集成电路结构的方法包括在单个多晶层中形成高价值电阻元件和低电阻互连。在一个实施例中，多晶硅层的互连区域被掩蔽，并且电阻元件区域被部分氧化以减小这些区域中的多晶层的厚度。然后可以通过在其中注入高水平的杂质或通过在互连区域上形成难熔金属硅化物层来减小互连区域的电阻率。在氧化过程中在电阻元件上形成的氧化物保护它们免于以下任一工艺步骤，从而不需要掩蔽。在替代实施例中，多晶硅层的互连区域的硅化可以在电阻元件区域的先前局部氧化的情况下进行。

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