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1. 发明授权

US4074150A MOS interchip receiver differential amplifiers employing resistor shunt CMOS amplifiers 失效
标题翻译：使用电阻分流CMOS放大器的MOS片间接收器差分放大器
公开(公告)号：US4074150A
公开(公告)日：1978-02-14
申请号：US701385
申请日：1976-06-30
申请人： Frederick Buckley, III , Malcom K. Creamer, Jr. , Gerald A. Miller
发明人： Frederick Buckley, III , Malcom K. Creamer, Jr. , Gerald A. Miller
IPC分类号： H03K19/0185 , H03K5/02 , H03K17/687 , H03K19/017 , H03K19/08 , H03K19/0948 , H03K5/20 , H03K17/04 , H03K17/60
CPC分类号： H03K5/023 , H03K19/017 , H03K19/08 , H03K19/0948
摘要： A negative shunt feedback CMOS amplifier is disclosed for connection to the output nodes of MOS interchip digital signal receiver differential amplifiers which have highly capacitive output nodes in order to bypass the large capacitance to thereby extract a high speed current signal. A first embodiment of the invention uses a resistor, to which this application is directed to, as the shunt feedback and a second embodiment of the invention uses parallel N-channel and P-channel FETs to form the shunt feedback impedance.
摘要翻译：公开了一种负分流反馈CMOS放大器，用于连接到具有高容性输出节点的MOS片上数字信号接收器差分放大器的输出节点，以绕过大电容从而提取高速电流信号。本发明的第一实施例使用该应用涉及的电阻器作为并联反馈，并且本发明的第二实施例使用并行N沟道FET和P沟道FET来形成并联反馈阻抗。

2. 发明授权

US4074151A MOS interchip receiver differential amplifiers employing CMOS amplifiers having parallel connected CMOS transistors as feedback shunt impedance paths 失效
标题翻译：采用具有并联CMOS晶体管的CMOS放大器作为反馈并联阻抗路径的MOS片间接收器差分放大器
公开(公告)号：US4074151A
公开(公告)日：1978-02-14
申请号：US701377
申请日：1976-06-30
申请人： Frederick Buckley, III , Gerald A. Miller , Vincent A. Scotto
发明人： Frederick Buckley, III , Gerald A. Miller , Vincent A. Scotto
IPC分类号： H03K19/0185 , H03K5/02 , H03K17/687 , H03K19/017 , H03K19/08 , H03K19/0948 , H03K5/20 , H03K17/04 , H03K17/60
CPC分类号： H03K5/023 , H03K19/017 , H03K19/08 , H03K19/0948
摘要： A negative shunt feedback CMOS amplifier is disclosed for connection to the output nodes of MOS interchip digital signal receiver differential amplifiers which have highly capacitive output nodes in order to bypass the large capacitance to thereby extract a high speed current signal. A first embodiment of the invention uses a resistor as the shunt feedback and a second embodiment of the invention, to which this application is directed to, uses parallel N-channel and P-channel FETs to form the shunt feedback impedance.
摘要翻译：公开了一种负分流反馈CMOS放大器，用于连接到具有高容性输出节点的MOS片上数字信号接收器差分放大器的输出节点，以绕过大电容从而提取高速电流信号。本发明的第一实施例使用电阻器作为并联反馈，并且本申请涉及的本发明的第二实施例使用并行N沟道和P沟道FET来形成并联反馈阻抗。

3. 发明授权

US5477082A Bi-planar multi-chip module 失效
标题翻译：双平面多芯片模块
公开(公告)号：US5477082A
公开(公告)日：1995-12-19
申请号：US179904
申请日：1994-01-11
申请人： Frederick Buckley, III , James S. Blomgren
发明人： Frederick Buckley, III , James S. Blomgren
IPC分类号： H01L23/538 , H01L25/16 , H01L23/12 , H01L23/488
CPC分类号： H01L25/16 , H01L23/5384 , H01L23/5387 , H01L2224/16 , H01L2924/01078 , H01L2924/01079 , H01L2924/10253 , H01L2924/15311 , H01L2924/1532 , H01L2924/16195
摘要： A bi-planar multi-chip package has die mounted on both sides of an insulating flexible carrier. The die are located in two parallel planes, with the flexible carrier located on a third plane between the two die planes. The die are mounted with the active circuit area facing each other on opposing sides of the flexible carrier. The carrier has conductive layers forming interconnect traces on both sides, and through-vias for connecting traces on opposite sides. The opposing die are mounted to the carrier with a solder-bump process with opposing pads located directly opposite each other. Vias are located in close proximity to the pads, between adjacent pads on the flexible carrier. Because the vias are between two adjacent pads, the interconnect length between two pads is on the order of the pad pitch. Thus opposing pads on the two die may be connected through the adjacent via with a small interconnect length.
摘要翻译：双平面多芯片封装具有安装在绝缘柔性载体两侧的裸片。模具位于两个平行的平面中，柔性载体位于两个模具平面之间的第三平面上。模具安装有活动电路区域在柔性载体的相对侧面对着。载体具有在两侧形成互连迹线的导电层和用于连接相对侧上的迹线的通孔。相对的管芯通过焊接凸块工艺安装到载体上，其中相对的焊盘彼此直接相对。通孔位于靠近垫片的位置，位于柔性载体上的相邻垫片之间。由于通孔位于两个相邻的焊盘之间，所以两个焊盘之间的互连长度是焊盘间距的数量级。因此，两个管芯上的相对的焊盘可以通过相邻的通孔以小的互连长度连接。

4. 发明授权

US3986041A CMOS digital circuits with resistive shunt feedback amplifier 失效
标题翻译：具有电阻分流反馈放大器的CMOS数字电路
公开(公告)号：US3986041A
公开(公告)日：1976-10-12
申请号：US534950
申请日：1974-12-20
申请人： Frederick Buckley, III , Malcom Kenneth Creamer, Jr. , Gerald Aberdeen Miller
发明人： Frederick Buckley, III , Malcom Kenneth Creamer, Jr. , Gerald Aberdeen Miller
IPC分类号： H03K19/0185 , H03K5/02 , H03K17/687 , H03K19/017 , H03K19/08 , H03K19/0948 , H03K19/32 , H03K19/34 , H03K19/36
CPC分类号： H03K5/023 , H03K19/017 , H03K19/08 , H03K19/0948
摘要： A negative shunt feedback amplifier is disclosed for connection to the output node of a complex complementary metal oxide semiconductor logic circuit to increase the performance and reduce the FET device size. A CMOS inverter is coupled to the amplifier to restore the logic levels and to form the logic output. A first embodiment of the invention uses a resistor feedback and a second embodiment of the invention uses parallel N-channel and P-channel FETs to form the feedback impedance. The circuit has application in environments where a logic function requires a large number of FET devices resulting in a large output node capacitance and, thereby slowing the logic speed, as for example in a large DOT-OR circuit or at each output of a FET memory array.
摘要翻译：公开了一种用于连接到复杂互补金属氧化物半导体逻辑电路的输出节点的负分流反馈放大器，以增加性能并降低FET器件尺寸。 CMOS反相器耦合到放大器以恢复逻辑电平并形成逻辑输出。本发明的第一实施例使用电阻器反馈，并且本发明的第二实施例使用并行N沟道和P沟道FET来形成反馈阻抗。该电路应用在逻辑功能需要大量FET器件的环境中，导致大的输出节点电容，从而减慢逻辑速度，例如在大DOT-OR电路中或在FET存储器的每个输出端数组。

5. 发明授权

US06563371B2 Current bandgap voltage reference circuits and related methods 有权
标题翻译：电流带隙电压参考电路及相关方法
公开(公告)号：US06563371B2
公开(公告)日：2003-05-13
申请号：US09939423
申请日：2001-08-24
申请人： Frederick Buckley, III , Paul D. Hildebrant
发明人： Frederick Buckley, III , Paul D. Hildebrant
IPC分类号： G05F110
CPC分类号： G05F3/30
摘要： A bandgap voltage reference circuit and related method characterized in having a first current source for generating a first current having a positive temperature coefficient, a second current source for generating a second current having a negative temperature coefficient, and a resistive element to receive both the first and second current to develop a reference voltage. By configuring the circuit such that the magnitudes of the positive and negative temperature coefficients are substantially the same, the reference voltage becomes substantially invariant with changes in temperature. Another circuit is provided in conjunction with the voltage reference circuit to substantially equalize the drain-to-source voltage of the transistors used in the voltage reference circuit.
摘要翻译：一种带隙电压参考电路及相关方法，其特征在于具有用于产生具有正温度系数的第一电流的第一电流源，用于产生具有负温度系数的第二电流的第二电流源和用于接收第一和第二电流来开发参考电压。通过配置电路使得正温度系数和负温度系数的大小基本上相同，参考电压随着温度的变化而变得基本上不变。结合电压参考电路提供另一个电路，以基本上均衡在电压参考电路中使用的晶体管的漏 - 源电压。

6. 发明授权

US5453949A BiCMOS Static RAM with active-low word line 失效
标题翻译： BiCMOS具有低电平有效字线的静态RAM
公开(公告)号：US5453949A
公开(公告)日：1995-09-26
申请号：US298593
申请日：1994-08-31
申请人： Siegfried Wiedmann , Frederick Buckley, III
发明人： Siegfried Wiedmann , Frederick Buckley, III
IPC分类号： G11C11/412 , G11C11/418 , G11C11/40
CPC分类号： G11C11/418 , G11C11/412
摘要： A static RAM memory is ideally suited for BiCMOS processes. As in standard CMOS memory cells, the cells have cross-coupled inverters that have more efficient n-channel transistors for the drive transistors, which pull a bit line low during a read operation. The weaker p-channel transistors are used for load transistors in the cross-coupled inverters, adding to cell stability while requiring no power. In contrast to prior-art cells, p-channel pass transistors are used. Common-emitter word-line drivers are also used that require a small input-voltage swing in comparison with the large word-line voltage swing. A low voltage on the word line selects a memory cell by causing p-channel pass transistors to conduct, coupling bit lines to the cross-coupled inverters in the memory cell. Power consumption is reduced since only one selected word line is at a low voltage, while the deselected word lines are at a high voltage. Common-emitter word-line drivers have a conduction path from the positive supply terminal to ground when the output word line is low, but no conduction path when the output word line is high. Thus only the common-emitter word-line driver that is connected to the selected low word line consumes appreciable power.
摘要翻译：静态RAM存储器非常适合BiCMOS工艺。与标准CMOS存储单元一样，这些单元具有交叉耦合的反相器，其具有用于驱动晶体管的更有效的n沟道晶体管，其在读取操作期间将位线拉低。较弱的p沟道晶体管用于交叉耦合的逆变器中的负载晶体管，增加了电池的稳定性，同时不需要电源。与现有技术的单元相反，使用p沟道传输晶体管。与大字线电压摆幅相比，也使用共发射极字线驱动器，需要较小的输入电压摆幅。字线上的低电压通过使p沟道传输晶体管导通，将位线耦合到存储单元中的交叉耦合的反相器来选择存储单元。由于只有一个选定的字线处于低电压，而取消选择的字线处于高电压，所以功耗降低。当输出字线为低电平时，共发射极字线驱动器具有从正电源端子接地的导通路径，而当输出字线为高电平时，则不具有导通路径。因此，只有连接到所选低字线的共发射极字线驱动器消耗明显的功率。

7. 发明授权

US3986043A CMOS digital circuits with active shunt feedback amplifier 失效
标题翻译：具有主动分流反馈放大器的CMOS数字电路
公开(公告)号：US3986043A
公开(公告)日：1976-10-12
申请号：US534945
申请日：1974-12-20
申请人： Frederick Buckley, III , Gerald Aberdeen Miller , Vincent Anthony Scotto
发明人： Frederick Buckley, III , Gerald Aberdeen Miller , Vincent Anthony Scotto
IPC分类号： H03K19/0185 , H03K5/02 , H03K17/687 , H03K19/017 , H03K19/08 , H03K19/0948 , H03K19/32 , H03K19/34 , H03K19/36
CPC分类号： H03K5/023 , H03K19/017 , H03K19/08 , H03K19/0948
摘要： A negative shunt feedback amplifier is disclosed for connection to the output node of a complex complementary metal oxide semiconductor logic circuit to increase the performance and reduce the FET device size. A CMOS inverter is coupled to the amplifier to restore the logic levels and to form the logic output. A first embodiment of the invention uses a resistor feedback and a second embodiment of the invention uses parallel N-channel and P-channel FETs to form the feedback impedance. The circuit has application in environments where a logic function requires a large number of FET devices resulting in a large output node capacitance and, thereby slowing the logic speed, as for example in a large DOT-OR circuit or at each output of a FET memory array.
摘要翻译：公开了一种用于连接到复杂互补金属氧化物半导体逻辑电路的输出节点的负分流反馈放大器，以增加性能并降低FET器件尺寸。 CMOS反相器耦合到放大器以恢复逻辑电平并形成逻辑输出。本发明的第一实施例使用电阻器反馈，并且本发明的第二实施例使用并行N沟道和P沟道FET来形成反馈阻抗。该电路应用在逻辑功能需要大量FET器件的环境中，导致大的输出节点电容，从而减慢逻辑速度，例如在大DOT-OR电路中或在FET存储器的每个输出端数组。

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