专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20100048152A1 MIXER CIRCUIT AND METHOD OF OPERATION 有权
标题翻译：混频器电路和操作方法
公开(公告)号：US20100048152A1
公开(公告)日：2010-02-25
申请号：US12306640
申请日：2007-06-15
申请人： Frederic F. Villain , Olivier Burg
发明人： Frederic F. Villain , Olivier Burg
IPC分类号： G06F3/033
CPC分类号： G06F7/58 , G06F7/584 , G06F2207/581 , G06F2207/583 , H03D7/1441 , H03D7/1458 , H03D7/1475 , H03D7/1483 , H03K3/84
摘要： A mixer circuit to mix a RF (Radio Frequency) signal with a LO (Local Oscillator) signal to generate an IF (Intermediate Frequency) signal including a dummy branch connected in parallel of a mixing branch, the dummy branch including a transconductance stage having an input connected to a reference potential independent from the RF signal, to transform the reference potential into a current signal, and a current switching core to switch the current signal according to LO and signals, and chopping switches to connect in series the transconductance stage of the mixing branch to the current switching core of the mixing branch and, in the alternative, to the current switching core of the dummy branch under the control of a chopping signal.
摘要翻译：一种用于将RF（射频）信号与LO（本地振荡器）信号混合以产生包括混合分支并联连接的虚拟分支的IF（中频）信号的混频器电路，所述虚拟分支包括跨导级，具有输入连接到独立于RF信号的参考电位，将参考电位变换为电流信号，以及电流切换磁芯，以根据LO和信号切换电流信号，以及斩波开关串联跨导级的跨导级混合分支到混合分支的当前交换核心，或者替代地，在斩波信号的控制下到虚拟分支的当前交换核心。

2. 发明授权

US08140044B2 Mixer circuit and method of operation 有权
标题翻译：搅拌机电路及操作方法
公开(公告)号：US08140044B2
公开(公告)日：2012-03-20
申请号：US12306640
申请日：2007-06-15
申请人： Frederic F. Villain , Olivier Burg
发明人： Frederic F. Villain , Olivier Burg
IPC分类号： H04B1/26
CPC分类号： G06F7/58 , G06F7/584 , G06F2207/581 , G06F2207/583 , H03D7/1441 , H03D7/1458 , H03D7/1475 , H03D7/1483 , H03K3/84
摘要： A mixer circuit to mix a RF (Radio Frequency) signal with a LO (Local Oscillator) signal to generate an IF (Intermediate Frequency) signal including a dummy branch connected in parallel of a mixing branch, the dummy branch including a transconductance stage having an input connected to a reference potential independent from the RF signal, to transform the reference potential into a current signal, and a current switching core to switch the current signal according to LO and signals, and chopping switches to connect in series the transconductance stage of the mixing branch to the current switching core of the mixing branch and, in the alternative, to the current switching core of the dummy branch under the control of a chopping signal.
摘要翻译：一种用于将RF（射频）信号与LO（本地振荡器）信号混合以产生包括混合分支并联连接的虚拟分支的IF（中频）信号的混频器电路，所述虚拟分支包括跨导级，具有输入连接到独立于RF信号的参考电位，将参考电位变换为电流信号，以及电流切换磁芯，以根据LO和信号切换电流信号，以及斩波开关串联跨导级的跨导级混合分支到混合分支的当前交换核心，或者替代地，在斩波信号的控制下到虚拟分支的当前交换核心。

3. 发明授权

US09036763B2 Methods and devices for implementing all-digital phase locked loop 有权
标题翻译：用于实现全数字锁相环的方法和装置
公开(公告)号：US09036763B2
公开(公告)日：2015-05-19
申请号：US13406342
申请日：2012-02-27
申请人： Olivier Burg , Miguel Kirsch
发明人： Olivier Burg , Miguel Kirsch
IPC分类号： H03D3/24 , H03L7/099 , H03L7/113 , H03L7/16
CPC分类号： H03L7/1976 , H03L7/0991 , H03L7/113 , H03L7/16 , H03L2207/50
摘要： An all-digital phase locked loop includes a time to digital converter that determines a fractional portion of a phase count. The time to digital converter has a quantization error that may be caused by phase noise, delay errors or skew errors. Several methods and devices may reduce the quantization error. A noise source may add dithering to the reference clock at an input of the time to digital converter. A digital processor may use two successive rising edges of the oscillator signal to count time delays of the time to digital convertor to the reference clock, and uses these counts to determine a ratio of the time delays and the time period of the oscillator signal for controlling a digitally controlled oscillator. A radio frequency counter circuit detects whether the oscillator signal leads or lags the reference clock because of skew and generates a phase signal to correct the skew.
摘要翻译：全数字锁相环包括确定相位数的分数部分的时间到数字转换器。数字转换器的时间具有可能由相位噪声，延迟误差或偏斜误差引起的量化误差。若干方法和装置可以减少量化误差。噪声源可能在时间到数字转换器的输入处将抖动添加到参考时钟。数字处理器可以使用振荡器信号的两个连续的上升沿来计算到数字转换器到参考时钟的时间的时间延迟，并且使用这些计数来确定用于控制的振荡器信号的时间延迟和时间周期的比率数字控制振荡器。射频计数器电路检测振荡器信号是否由于偏斜引起或滞后于参考时钟，并产生相位信号以纠正偏斜。

4. 发明授权

US06801081B2 Switching device provided with integrated test means 失效
标题翻译：交换设备提供集成的测试手段
公开(公告)号：US06801081B2
公开(公告)日：2004-10-05
申请号：US10299276
申请日：2002-11-19
申请人： Gilbert Gloaguen , Olivier Burg , Bassem Fahs
发明人： Gilbert Gloaguen , Olivier Burg , Bassem Fahs
IPC分类号： G06G712
CPC分类号： H04L49/555 , H04L49/101
摘要： The invention relates to a switching device comprising a matrix having connection points and integrated test means comprising two pairs of generators/detectors which are pairwise controlled in such a way that the transmission paths traversed by the RF test signals from the generators to the associated inputs of the matrix and from the outputs of the matrix and to the associated detector are of the order of length of a single side of the switching matrix.
摘要翻译：本发明涉及一种包括具有连接点的矩阵和集成测试装置的开关装置，所述集成测试装置包括两对发生器/检测器，这两对发生器/检测器成对地被控制，使得由来自发生器的RF测试信号穿过的传输路径到相关联的输入矩阵和从矩阵的输出到相关联的检测器的矩阵是开关矩阵的单侧的长度的数量级。

5. 发明授权

US08710884B2 Methods and devices for multiple-mode radio frequency synthesizers 有权
标题翻译：多模射频合成器的方法和装置
公开(公告)号：US08710884B2
公开(公告)日：2014-04-29
申请号：US13406246
申请日：2012-02-27
申请人： Olivier Burg , Cao-Thong Tu
发明人： Olivier Burg , Cao-Thong Tu
IPC分类号： H03L7/00
CPC分类号： H03L7/1976 , H03L7/0991 , H03L7/113 , H03L7/16 , H03L2207/50
摘要： Methods and devices provide for determining whether to operate a radio frequency synthesizer in a first mode of operation or a second mode of operation based on a reference frequency signal. The radio frequency synthesizer includes a digitally-controlled oscillator configured to generate an oscillator signal having an output frequency. A digital frequency locked-loop is configured to control the output frequency of the oscillator signal in a first mode of operation based on a first control signal. A digital phase locked-loop is configured to control the output frequency of the oscillator signal in a second mode of operation based on a second control signal. A controller determines whether to operate in the first mode or second mode based on a reference frequency signal. The controller generates the first or second control signal based on the determination of operating in the first or second mode, respectively.
摘要翻译：方法和装置提供用于基于参考频率信号来确定是否在第一操作模式或第二操作模式中操作射频合成器。射频合成器包括配置成产生具有输出频率的振荡器信号的数字控制振荡器。数字频率锁定环被配置为基于第一控制信号来控制处于第一操作模式的振荡器信号的输出频率。数字锁相环被配置为基于第二控制信号在第二操作模式中控制振荡器信号的输出频率。控制器基于参考频率信号来确定是否在第一模式或第二模式中操作。控制器基于分别在第一或第二模式中的操作的确定来产生第一或第二控制信号。

6. 发明申请

US20120328065A1 Methods and Devices for Implementing All-Digital Phase Locked Loop 有权
标题翻译：实现全数字锁相环的方法和装置
公开(公告)号：US20120328065A1
公开(公告)日：2012-12-27
申请号：US13406342
申请日：2012-02-27
申请人： Olivier Burg , Miguel Kirsch
发明人： Olivier Burg , Miguel Kirsch
IPC分类号： H03D3/24
CPC分类号： H03L7/1976 , H03L7/0991 , H03L7/113 , H03L7/16 , H03L2207/50
摘要： An all-digital phase locked loop includes a time to digital converter that determines a fractional portion of a phase count. The time to digital converter has a quantization error that may be caused by phase noise, delay errors or skew errors. Several methods and devices may reduce the quantization error. A noise source may add dithering to the reference clock at an input of the time to digital converter. A digital processor may use two successive rising edges of the oscillator signal to count time delays of the time to digital convertor to the reference clock, and uses these counts to determine a ratio of the time delays and the time period of the oscillator signal for controlling a digitally controlled oscillator. A radio frequency counter circuit detects whether the oscillator signal leads or lags the reference clock because of skew and generates a phase signal to correct the skew.
摘要翻译：全数字锁相环包括确定相位数的分数部分的时间到数字转换器。数字转换器的时间具有可能由相位噪声，延迟误差或偏斜误差引起的量化误差。若干方法和装置可以减少量化误差。噪声源可能在时间到数字转换器的输入处将抖动添加到参考时钟。数字处理器可以使用振荡器信号的两个连续的上升沿来计算到数字转换器到参考时钟的时间的时间延迟，并且使用这些计数来确定用于控制的振荡器信号的时间延迟和时间周期的比率数字控制振荡器。射频计数器电路检测振荡器信号是否由于偏斜引起或滞后于参考时钟，并产生相位信号以纠正偏斜。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式