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1. 发明授权

US4740479A Method for the manufacture of cross-couplings between n-channel and p-channel CMOS field effect transistors of static write-read memories 失效
标题翻译：用于制造静态写入存储器的n沟道和p沟道CMOS场效应晶体管之间的交叉耦合的方法
公开(公告)号：US4740479A
公开(公告)日：1988-04-26
申请号：US874698
申请日：1986-06-16
申请人： Franz Neppl , Konrad Hieber , Ulrich Schwabe, deceased
发明人： Franz Neppl , Konrad Hieber , Ulrich Schwabe, deceased
IPC分类号： H01L27/11 , H01L21/768 , H01L21/8234 , H01L21/8238 , H01L21/8244 , H01L21/8247 , H01L27/088 , H01L27/092 , H01L27/10 , H01L27/11517 , H01L29/78
CPC分类号： H01L27/11517 , H01L21/76889 , H01L21/823871 , H01L21/823878 , H01L27/1104 , Y10S257/903
摘要： Cross-couplings between n-channel and p-channel CMOS field effect transistors of static write-read memories (SRAMs) with buried contacts to the n.sup.+ and p.sup.+ regions in the substrate are obtained in accordance with known method steps and with a high packing density. A gate level thereof formed of a polycide double layer is used as an additional wiring level for the cross-coupling. The formation of the gate level occurs after the opening of regions for the buried contacts. A doping occurs simultaneously with the generation of source/drain regions of the n-channel and p-channel transistors by masked ion implantation and a subsequent high-temperature treatment. Accordingly, simple, mask-non-intensive method steps result which are especially useful in the manufacture of 6-transistor SRAMs.
摘要翻译：根据已知的方法步骤获得具有与衬底中的n +和p +区的埋入触点的静态写入存储器（SRAM）的n沟道和p沟道CMOS场效应晶体管之间的交叉耦合，并具有高的堆积密度。由多晶硅双层形成的栅极层用作交叉耦合的附加布线水平。栅极电平的形成发生在埋入触点的区域开放之后。通过掩模离子注入和随后的高温处理与n沟道和p沟道晶体管的源极/漏极区的产生同时发生掺杂。因此，在制造6晶体管SRAM时特别有用的简单的掩模非密集方法步骤。

2. 发明授权

US4510670A Method for the manufacture of integrated MOS-field effect transistor circuits silicon gate technology having diffusion zones coated with silicide as low-impedance printed conductors 失效
标题翻译：用于制造集成MOS场效应晶体管电路的硅栅极技术，其具有涂覆有硅化物作为低阻抗印刷导体的扩散区
公开(公告)号：US4510670A
公开(公告)日：1985-04-16
申请号：US458533
申请日：1983-01-17
申请人： Ulrich Schwabe , Franz Neppl , Konrad Hieber
发明人： Ulrich Schwabe , Franz Neppl , Konrad Hieber
IPC分类号： H01L29/78 , H01L21/28 , H01L21/285 , H01L21/336 , H01L21/768 , H01L29/45 , H01L29/49
CPC分类号： H01L29/66515 , H01L21/28061 , H01L21/28518 , H01L21/76879 , H01L21/76889 , H01L29/41783 , H01L29/456 , H01L29/4933 , H01L29/66575 , H01L29/66545
摘要： A method for the manufacture of integrated MOS-field effect transistor circuits in silicon gate technology and wherein diffusion source and drain zones are coated with a high melting point silicide as low-impedance printed conductors. The diffusion zones and polysilicon gates are made low-impedance through selective deposition of the metal silicide onto surfaces thereof. The selective deposition, which proceeds by use of a reaction gas eliminating hydrogen halide, simplifies the process sequence and is fully compatible with conventional silicon gate processes. Because of the high temperature stability, preferably tantalum silicide is employed. The invention is useful in the manufacture of MOS-circuits in VLSI-technology.
摘要翻译：一种用于在硅栅极技术中制造集成MOS场效应晶体管电路的方法，其中扩散源极和漏极区域被涂覆有高熔点硅化物作为低阻抗印刷导体。通过将金属硅化物选择性沉积到其表面上，扩散区和多晶硅栅极被制成低阻抗。通过使用消除卤化氢的反应气体进行的选择性沉积简化了工艺顺序，并且与传统的硅浇口工艺完全兼容。由于高温稳定性，所以优选采用硅化钽。本发明可用于制造VLSI技术中的MOS电路。

3. 发明授权

US4680612A Integrated semiconductor circuit including a tantalum silicide diffusion barrier 失效
标题翻译：包括硅化钽扩散阻挡层的集成半导体电路
公开(公告)号：US4680612A
公开(公告)日：1987-07-14
申请号：US843380
申请日：1986-03-24
申请人： Konrad Hieber , Franz Neppl , Konrad Schober
发明人： Konrad Hieber , Franz Neppl , Konrad Schober
IPC分类号： H01L29/43 , H01L21/28 , H01L23/532 , H01L23/48
CPC分类号： H01L23/53223 , H01L2924/0002 , H01L2924/3011 , Y10T428/12528 , Y10T428/12743 , Y10T428/12819
摘要： An integrated semiconductor circuit consisting of a silicon substrate having an impurity doped circuit therein, and a layer of silicon dioxide formed on the substrate and having a contact hole therein overlying the circuit. An outer contact interconnect level composed of aluminum or an aluminum alloy provides electrical contact to the circuit. A tantalum disilicide diffusion barrier layer is disposed between the circuit and the interconnect level, with a layer of substantially pure tantalum both above and below the tantalum disilicide diffusion barrier layer.
摘要翻译：由其中具有杂质掺杂电路的硅衬底和形成在衬底上的二氧化硅层组成的集成半导体电路，其中覆盖电路的接触孔。由铝或铝合金组成的外部接触互连层提供与电路的电接触。二硅化钛扩散阻挡层设置在电路和互连层之间，在二硅化硅扩散阻挡层的上方和下方具有基本上纯的钽层。

4. 发明授权

US4673968A Integrated MOS transistors having a gate metallization composed of tantalum or niobium or their silicides 失效
标题翻译：具有由钽或铌组成的栅极金属化或其硅化物的集成MOS晶体管
公开(公告)号：US4673968A
公开(公告)日：1987-06-16
申请号：US866951
申请日：1986-05-27
申请人： Konrad Hieber , Franz Neppl
发明人： Konrad Hieber , Franz Neppl
IPC分类号： H01L29/78 , H01L21/28 , H01L21/3205 , H01L29/423 , H01L29/43 , H01L29/49 , H01L23/48
CPC分类号： H01L29/4966 , H01L21/28079 , H01L21/28097 , H01L21/32051 , H01L29/495 , H01L29/4975
摘要： Chemical reactions between a tantalum or tantalum silicide metallization layer and an underlying thin gate oxide are avoided by the interposition of an intermediate layer of oxygen-doped tantalum or tantalum silicide whose thickness amounts to about 1/20 to 1/5 of the layer thickness of the entire gate metallization. The metallization layer is produced by high-frequency sputtering in which oxygen is added at the beginning of the process and argon is used as a sputtering gas. Low specific resistance values are accomplished by means of this gate metallization.
摘要翻译：通过插入掺杂氧的钽或硅化钽的中间层来避免钽或钽硅化物金属化层和下面的薄栅极氧化物之间的化学反应，其厚度约为层厚度的1/20至1/5 整个栅极金属化。金属化层是通过高温溅射法生产的，其中在工艺开始时加入氧气，氩气用作溅射气体。低电阻值通过该栅极金属化实现。

5. 发明授权

US4640844A Method for the manufacture of gate electrodes formed of double layers of metal silicides having a high melting point and doped polycrystalline silicon 失效
标题翻译：用于制造由具有高熔点和掺杂多晶硅的双层金属硅化物形成的栅电极的方法
公开(公告)号：US4640844A
公开(公告)日：1987-02-03
申请号：US709712
申请日：1985-03-08
申请人： Franz Neppl , Ulrich Schwabe , Konrad Hieber
发明人： Franz Neppl , Ulrich Schwabe , Konrad Hieber
IPC分类号： H01L27/092 , H01L21/28 , H01L21/3205 , H01L21/3215 , H01L21/336 , H01L21/8234 , H01L21/8238 , H01L23/52 , H01L27/088 , H01L29/423 , H01L29/43 , H01L29/49 , H01L29/78 , B05D5/12 , C23C16/00
CPC分类号： H01L21/32155 , H01L21/823835 , H01L29/4933
摘要： A method for manufacture of gate electrodes formed of double layers of metal silicides having a high melting point and doped polycrystalline silicon. The polycystalline silicon is deposited in undoped fashion before the metal silicide and the doping of the silicon is obtained through the production of the source/drain-zones through ion implantation and a subsequent high temperature step. The method permits the problem-free manufacture of polycide-gates with n.sup.+ - and p.sup.+ -polysilicon on a chip without increased technological expense. Planarization is facilitated through the thin gate layers. The method is used in the manufacture of highly integrated CMOS-circuits.
摘要翻译：一种用于制造由具有高熔点和掺杂多晶硅的双层金属硅化物形成的栅电极的方法。在金属硅化物之前以未掺杂的方式沉积多晶硅，并且通过离子注入和随后的高温步骤通过产生源极/漏极区获得硅的掺杂。该方法允许在芯片上无问题地制造具有n +和p + - 多晶硅的多晶硅栅极，而不增加技术费用。通过薄栅层促进平面化。该方法用于制造高度集成的CMOS电路。

6. 发明授权

US5399389A Method for locally and globally planarizing chemical vapor deposition of SiO.sub.2 layers onto structured silicon substrates 失效
标题翻译：将SiO 2层的化学气相沉积局部和全局平面化到结构化硅衬底上的方法
公开(公告)号：US5399389A
公开(公告)日：1995-03-21
申请号：US94337
申请日：1993-07-20
申请人： Konrad Hieber , Jasper Von Tomkewitsch , Oswald Spindler , Helmuth Treichel , Zvonimir Gabric , Alexander Gschwandtner
发明人： Konrad Hieber , Jasper Von Tomkewitsch , Oswald Spindler , Helmuth Treichel , Zvonimir Gabric , Alexander Gschwandtner
IPC分类号： C30B29/18 , H01L21/316 , H01L21/3205 , H01L21/768 , B05D3/06 , H01L21/02
CPC分类号： H01L21/02164 , H01L21/02216 , H01L21/02271 , H01L21/02304 , H01L21/02315 , H01L21/31612 , H01L21/76819
摘要： In the ozone-activated deposition of insulating layers, different growth rates can be achieved on differently constituted surfaces. When the surfaces of the structured silicon substrates lying at different levels are differently constituted or, respectively, are intentionally varied such that the SiO.sub.2 insulating layer grows more slowly on the higher surfaces than on the more deeply disposed surfaces and when deposition is carried out until the surfaces of the rapidly growing and slowly growing layer regions form a step-free, planar level, a local and global planarization is achieved.
摘要翻译：在绝缘层的臭氧活化沉积中，可以在不同构造的表面上实现不同的生长速率。当不同层次的结构硅衬底的表面被不同地构成或分别有意地改变，使得SiO 2绝缘层在较高表面上比在更深的设置表面上更缓慢地生长，并且当沉积被执行直到快速生长和缓慢生长的层区域的表面形成无梯度的平面水平，实现局部和全局平坦化。

7. 发明授权

US4767496A Method for controlling and supervising etching processes 失效
标题翻译：控制和监督蚀刻工艺的方法
公开(公告)号：US4767496A
公开(公告)日：1988-08-30
申请号：US113829
申请日：1987-10-29
申请人： Konrad Hieber
发明人： Konrad Hieber
IPC分类号： H01L21/66 , C23F1/02 , C23F4/00 , G01B7/06 , H01J37/32 , H01L21/302 , H01L21/3065 , H01L21/3205 , H01L21/3213 , B44C1/22
CPC分类号： H01J37/32935 , C23F4/00
摘要： A method for controlling and supervising etching processes effected by ions, radicals, and/or neutral particles activated in a plasma includes identifying the etching rate and the final point of material erosion by the use of a reference substrate having a defined specimen geometry and situated on a moveable substrate holder in a recipient compartment or etching chamber. The electrical resistance of the specimen, which is dependent on the layer thickness of an electrically conductive layer, is measured and the measured data is transmitted in non-contacting fashion by electromagnetic radiation using pulse code modulation methods. A telemetric metrology system is used which is mounted on the moveable substrate holder as an independent unit. A process control computer supervises and, if need be, controls the etching parameters in the plasma.
摘要翻译：用于控制和监督在等离子体中激活的离子，自由基和/或中性粒子影响的蚀刻工艺的方法包括通过使用具有限定的样本几何形状的参考基底来识别蚀刻速率和最终的材料侵蚀点，并且位于接收室或蚀刻室中的可移动衬底保持器。测量取决于导电层的层厚度的试样的电阻，并且使用脉冲编码调制方法通过电磁辐射以非接触方式传输测量数据。使用遥测计量系统作为独立单元安装在可移动的基板支架上。过程控制计算机监督并且如果需要的话，控制等离子体中的蚀刻参数。

8. 发明授权

US4294871A Method for depositing a layer on the inside of cavities of a work piece 失效
标题翻译：在工件的腔体内部沉积层的方法
公开(公告)号：US4294871A
公开(公告)日：1981-10-13
申请号：US71685
申请日：1979-08-29
申请人： Konrad Hieber , Manfred Stolz
发明人： Konrad Hieber , Manfred Stolz
IPC分类号： C23C16/04 , C23C16/44 , C23C16/455 , C23C11/00
CPC分类号： C23C16/45504 , C23C16/045 , C23C16/455
摘要： Disclosed herein is a process for the chemical deposition of a material layer on the inside of cavities of a work piece by conducting a gas stream in a substantially laminar flow along a heated work piece wherein deposition occurs from the gaseous phase, at a pressure of less than 10.sup.4 Pascal (N/m.sup.2).
摘要翻译：本文公开了一种用于通过沿着加热的工件沿基本上层流的气流导入材料层的化学沉积的方法，其中沉积从气相以较小的压力发生超过104帕斯卡（N / m2）。

9. 发明授权

US4501769A Method for selective deposition of layer structures consisting of silicides of HMP metals on silicon substrates and products so-formed 失效
标题翻译：用于选择性沉积由硅衬底上的HMP金属的硅化物构成的层结构和如此形成的产品的层结构的选择性沉积
公开(公告)号：US4501769A
公开(公告)日：1985-02-26
申请号：US465299
申请日：1983-02-09
申请人： Konrad Hieber , Claudia Wieczorek
发明人： Konrad Hieber , Claudia Wieczorek
IPC分类号： C01B33/06 , C23C16/04 , C23C16/42 , H01L21/28 , H01L21/285 , B05D5/12 , C23C11/08
CPC分类号： H01L21/28518 , C23C16/04 , C23C16/42 , H01L21/28061
摘要： Structured layers composed of high melting point metal silicides, such as tantalum silicide, are selectively deposited on substrates having at least some silicon and some non-silicon regions, such as are used in thin-film and semiconductor technology, by thermal decomposition of gaseous silicon and halogen compounds containing a high melting point metal in a reaction gas and depositing the metal silicide onto the silicon regions of the substrates while providing a gaseous hydrogen halide, such as hydrogen chloride, to the reaction gas and adjusting the substrate deposition temperature and the composition of the reaction gas to values at which a silicide nucleation in substrate regions, other than silicon regions, is suppressed during deposition of the metal silicide from the gaseous phase due to the presence of the hydrogen halide. The invention is useful for producing contact track levels in VLSI circuits.
摘要翻译：由诸如硅化钽之类的高熔点金属硅化物构成的结构化层被选择性沉积在具有至少一些硅和一些非硅区域的基底上，例如用于薄膜和半导体技术中的气态硅的热分解和在反应气体中含有高熔点金属的卤素化合物，并将金属硅化物沉积到基板的硅区上，同时向反应气体提供气态卤化氢，并调节基板沉积温度和组成的反应气体与由于卤化氢的存在而在金属硅化物从气相沉积期间抑制了除了硅区域之外的衬底区域中的硅化物成核的值。本发明对于在VLSI电路中产生接触轨迹电平是有用的。

10. 发明授权

US4331702A Method for reproducible manufacture of metallic layers 失效
标题翻译：可重复制造金属层的方法
公开(公告)号：US4331702A
公开(公告)日：1982-05-25
申请号：US231885
申请日：1981-02-05
申请人： Konrad Hieber , Norbert Mayer
发明人： Konrad Hieber , Norbert Mayer
IPC分类号： C23C14/14 , C23C14/54 , G01B21/08 , H01L21/3205 , C23C13/02 , C23C15/00
CPC分类号： G01B21/08 , C23C14/545 , C23C14/546
摘要： Reproducible manufacture of metallic layers for semiconductor and thin film technology is attained by dynamic control of the layering process whereby the specific electrical resistance, .rho., is determined as a function of layer thickness, d, and layering parameters are regulated by a process-control computer. With this process, factors effecting the growth of a layer with respect to its structure, texture and composition are identified and calculated as measured values of .rho. and d, by the process-control computer and corrections for individual layering parameters are calculated via a suitable control program. In this manner, the nucleation of a layer and its growth is influenced in such a manner that the layer exhibits the desired electrical, structural and texture properties in its final state.
摘要翻译：用于半导体和薄膜技术的金属层的可再生制造通过层压工艺的动态控制来实现，其中比电阻rho被确定为层厚度d的函数，并且分层参数由过程控制计算机。通过该过程，通过过程控制计算机识别和计算影响层的生长相关于其结构，纹理和组成的因素，并通过过程控制计算机计算出rho和d的测量值，并通过适当的控制来计算各个分层参数的校正程序。以这种方式，层的成核和其生长以这样的方式受到影响，使得该层在其最终状态下表现出期望的电，结构和纹理性质。

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