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1. 发明申请

US20110047322A1 METHODS, SYSTEMS AND DEVICES FOR INCREASING DATA RETENTION ON SOLID-STATE MASS STORAGE DEVICES 审中-公开
标题翻译：在固态大量存储设备上增加数据保持的方法，系统和设备
公开(公告)号：US20110047322A1
公开(公告)日：2011-02-24
申请号：US12859557
申请日：2010-08-19
申请人： William J. Allen , Franz Michael Schuette
发明人： William J. Allen , Franz Michael Schuette
IPC分类号： G06F12/02 , G06F12/00
CPC分类号： G11C16/10 , G11C16/349
摘要： Methods, systems and devices for increasing the reliability of solid state drives containing one or more NAND flash memory arrays. The methods, systems and devices take into account usage patterns that can be employed to initiate proactive scrubbing on demand, wherein the demand is automatically generated by a risk index that can be based on one or more of various factors that typically contribute to loss of data retention in NAND flash memory devices.
摘要翻译：用于增加包含一个或多个NAND快闪存储器阵列的固态驱动器的可靠性的方法，系统和装置。方法，系统和设备考虑到可以用于按需启动主动洗涤的使用模式，其中需求由风险指数自动生成，风险指数可以基于通常有助于数据丢失的各种因素中的一种或多种保留在NAND闪存设备中。

2. 发明申请

US20100142247A1 MEMORY MODULES AND METHODS FOR MODIFYING MEMORY SUBSYSTEM PERFORMANCE 有权
标题翻译：用于修改存储器子系统性能的存储器模块和方法
公开(公告)号：US20100142247A1
公开(公告)日：2010-06-10
申请号：US12632176
申请日：2009-12-07
申请人： Franz Michael Schuette , William J. Allen
发明人： Franz Michael Schuette , William J. Allen
IPC分类号： G11C5/02 , G11C5/14
CPC分类号： G11C5/063 , G11C5/04 , G11C5/14 , H05K1/0262 , H05K1/117 , H05K2201/093 , H05K2201/09663 , H05K2201/10159
摘要： Methods and memory modules adapted for use in computer systems to generate different voltages for core supply (VDD) and input/output supply (VDDQ) inputs to memory components of the computer memory subsystem. The memory module includes a substrate with an edge connector, a memory component, and first and second voltage planes adapted to supply the core supply voltage and the input/output supply voltage to the memory component. The first voltage plane receives a system input voltage from the edge connector, and the second voltage plane is connected to the first voltage plane to receive a second voltage that is either higher or lower than the system input voltage. One of the first and second voltage planes is connected to the memory component to supply the core supply voltage thereto, and the other voltage plane supplies the input/output supply voltage to the memory component.
摘要翻译：适用于计算机系统的方法和存储器模块，用于为计算机存储器子系统的存储器组件产生用于核心电源（VDD）和输入/输出电源（VDDQ）输入的不同电压。存储器模块包括具有边缘连接器的基板，存储器部件以及适于将核心电源电压和输入/输出电源电压提供给存储器部件的第一和第二电压平面。第一电压平面从边缘连接器接收系统输入电压，并且第二电压平面连接到第一电压平面以接收高于或低于系统输入电压的第二电压。第一和第二电压平面中的一个连接到存储器组件以向其提供核心电源电压，而另一个电压平面将输入/输出电源电压提供给存储器组件。

3. 发明授权

US08375162B2 Method and apparatus for reducing write cycles in NAND-based flash memory devices 有权
标题翻译：用于减少基于NAND的闪存器件中的写周期的方法和装置
公开(公告)号：US08375162B2
公开(公告)日：2013-02-12
申请号：US12793023
申请日：2010-06-03
申请人： William J. Allen , Franz Michael Schuette
发明人： William J. Allen , Franz Michael Schuette
IPC分类号： G06F12/00
CPC分类号： G06F12/0246 , G06F2212/7201
摘要： A NAND-based flash memory device and a method of its operation that extends the life of the device by reducing the number of unnecessary write cycles to the device. The memory device includes blocks, pages contained by each of the blocks, and a page abstraction layer containing a look-up table for translating logical page numbers into physical page numbers. A certain number of the pages in at least one of the blocks is preferably reserved so as not to be used in default data storage mode but instead used to shuffle data within the at least one block using a dynamic page address scheme, whereby data are dynamically moved from one page to an empty page in the same block using dynamic page mapping.
摘要翻译：一种基于NAND的闪速存储器件及其操作方法，通过减少对器件的不必要的写入周期的数量来延长器件的使用寿命。存储器件包括块，由每个块包含的页面，以及包含用于将逻辑页码翻译成物理页码的查找表的页面抽象层。优选地，保留至少一个块中的一些页面，以便不在默认数据存储模式中使用，而是使用动态页面地址方案来混洗至少一个块内的数据，由此数据是动态的使用动态页面映射在同一个块中从一个页面移动到一个空页面。

4. 发明授权

US08164935B2 Memory modules and methods for modifying memory subsystem performance 有权
标题翻译：用于修改内存子系统性能的内存模块和方法
公开(公告)号：US08164935B2
公开(公告)日：2012-04-24
申请号：US12632176
申请日：2009-12-07
申请人： Franz Michael Schuette , William J. Allen
发明人： Franz Michael Schuette , William J. Allen
IPC分类号： G11C5/02 , G11C17/18
CPC分类号： G11C5/063 , G11C5/04 , G11C5/14 , H05K1/0262 , H05K1/117 , H05K2201/093 , H05K2201/09663 , H05K2201/10159
摘要： Methods and memory modules adapted for use in computer systems to generate different voltages for core supply (VDD) and input/output supply (VDDQ) inputs to memory components of the computer memory subsystem. The memory module includes a substrate with an edge connector, a memory component, and first and second voltage planes adapted to supply the core supply voltage and the input/output supply voltage to the memory component. The first voltage plane receives a system input voltage from the edge connector, and the second voltage plane is connected to the first voltage plane to receive a second voltage that is either higher or lower than the system input voltage. One of the first and second voltage planes is connected to the memory component to supply the core supply voltage thereto, and the other voltage plane supplies the input/output supply voltage to the memory component.
摘要翻译：适用于计算机系统的方法和存储器模块，用于为计算机存储器子系统的存储器组件产生用于核心电源（VDD）和输入/输出电源（VDDQ）输入的不同电压。存储器模块包括具有边缘连接器的基板，存储器部件以及适于将核心电源电压和输入/输出电源电压提供给存储器部件的第一和第二电压平面。第一电压平面从边缘连接器接收系统输入电压，并且第二电压平面连接到第一电压平面以接收高于或低于系统输入电压的第二电压。第一和第二电压平面中的一个连接到存储器组件以向其提供核心电源电压，而另一个电压平面将输入/输出电源电压提供给存储器组件。

5. 发明申请

US20100312953A1 METHOD AND APPARATUS FOR REDUCING WRITE CYCLES IN NAND-BASED FLASH MEMORY DEVICES 有权
标题翻译：用于减少基于NAND的闪速存储器件中的写入循环的方法和装置
公开(公告)号：US20100312953A1
公开(公告)日：2010-12-09
申请号：US12793023
申请日：2010-06-03
申请人： William J. Allen , Franz Michael Schuette
发明人： William J. Allen , Franz Michael Schuette
IPC分类号： G06F12/10 , G06F12/00
CPC分类号： G06F12/0246 , G06F2212/7201
摘要： A NAND-based flash memory device and a method of its operation that extends the life of the device by reducing the number of unnecessary write cycles to the device. The memory device includes blocks, pages contained by each of the blocks, and a page abstraction layer containing a look-up table for translating logical page numbers into physical page numbers. A certain number of the pages in at least one of the blocks is preferably reserved so as not to be used in default data storage mode but instead used to shuffle data within the at least one block using a dynamic page address scheme, whereby data are dynamically moved from one page to an empty page in the same block using dynamic page mapping.
摘要翻译：一种基于NAND的闪速存储器件及其操作方法，通过减少对器件的不必要的写入周期的数量来延长器件的使用寿命。存储器件包括块，由每个块包含的页面，以及包含用于将逻辑页码翻译成物理页码的查找表的页面抽象层。优选地，保留至少一个块中的一些页面，以便不在默认数据存储模式中使用，而是使用动态页面地址方案来混洗至少一个块内的数据，由此数据是动态的使用动态页面映射在同一个块中从一个页面移动到一个空页面。

6. 发明申请

US20100325352A1 HIERARCHICALLY STRUCTURED MASS STORAGE DEVICE AND METHOD 审中-公开
标题翻译：分层结构的大容量存储设备和方法
公开(公告)号：US20100325352A1
公开(公告)日：2010-12-23
申请号：US12815661
申请日：2010-06-15
申请人： Franz Michael Schuette , William J. Allen
发明人： Franz Michael Schuette , William J. Allen
IPC分类号： G06F12/02 , G06F12/08 , G06F13/00
CPC分类号： G06F12/0866 , G06F3/0613 , G06F3/0616 , G06F3/0647 , G06F3/0685 , G06F3/0688 , G06F12/0246 , G06F12/08 , G06F2212/214 , G06F2212/463 , G06F2212/7202
摘要： A hierarchically-structured computer mass storage system and method. The mass storage system includes a mass storage memory drive, control logic on the mass storage memory drive that includes a controller and one or more devices for executing a hierarchical storage management technique, a volatile memory cache configured to be accessed by the control logic, and first and second non-volatile storage arrays on the mass storage memory drive and comprising, respectively, first and second non-volatile memory devices. The first and second non-volatile memory devices have properties including access times and write endurance, and at least one of the access time and the write endurance of the first non-volatile memory devices is faster or higher, respectively, than the second non-volatile memory devices. Desired data storage localities on the storage arrays are determined through access patterns and selectively utilizing the properties of the memory devices to match the data storage requirements.
摘要翻译：分层结构的计算机大容量存储系统和方法。大容量存储系统包括大容量存储器驱动器，大容量存储器驱动器上的控制逻辑，其包括控制器和用于执行分层存储管理技术的一个或多个设备，被配置为被控制逻辑访问的易失性存储器高速缓存器，以及大容量存储器驱动器上的第一和第二非易失性存储阵列，并且分别包括第一和第二非易失性存储器件。第一和第二非易失性存储器件具有包括访问时间和写入耐久性的特性，并且第一非易失性存储器件的访问时间和写入耐久性中的至少一个分别比第二非易失性存储器设备更快或更高，易失性存储器件。通过访问模式确定存储阵列上所需的数据存储区域，并选择性地利用存储器件的属性来匹配数据存储要求。

7. 发明授权

US08949509B2 Mass storage systems and methods using solid-state storage media and ancillary interfaces for direct communication between memory cards 有权
标题翻译：使用固态存储介质的大容量存储系统和方法以及用于存储卡之间的直接通信的辅助接口
公开(公告)号：US08949509B2
公开(公告)日：2015-02-03
申请号：US13311723
申请日：2011-12-06
申请人： Franz Michael Schuette
发明人： Franz Michael Schuette
IPC分类号： G06F13/00 , G06F3/06 , G06F13/40
CPC分类号： G06F3/061 , G06F3/0658 , G06F3/0659 , G06F3/0688 , G06F13/40
摘要： A mass storage system comprising multiple memory cards, each with non-volatile memory components, a system bus interface for communicating with a system bus of a host system, and at least one ancillary interface. The ancillary interface is configured for direct communication of commands, addresses and data between the memory cards via a cross-link connector without accessing the system bus interface.
摘要翻译：一种大容量存储系统，包括多个存储卡，每个具有非易失性存储器组件，用于与主机系统的系统总线通信的系统总线接口以及至少一个辅助接口。辅助接口被配置为通过交叉连接器直接通信存储卡之间的命令，地址和数据，而不需要访问系统总线接口。

8. 发明授权

US08566669B2 Memory system and method for generating and transferring parity information 有权
标题翻译：用于生成和传送奇偶校验信息的存储器系统和方法
公开(公告)号：US08566669B2
公开(公告)日：2013-10-22
申请号：US13177839
申请日：2011-07-07
申请人： Franz Michael Schuette
发明人： Franz Michael Schuette
IPC分类号： G11C29/00 , G06F12/00 , G06F12/02 , G06F13/00 , G06F13/28
CPC分类号： G06F11/1048
摘要： A memory system and method for generating and transferring parity information within burst transactions of burst read and write transfers and without dedicated parity chips or parity data lines.
摘要翻译：一种用于在突发读和写传输的突发事务中产生和传送奇偶校验信息并且没有专用奇偶校验芯片或奇偶校验数据线的存储器系统和方法。

9. 发明授权

US08489966B2 Solid-state mass storage device and method for failure anticipation 有权
标题翻译：固态大容量存储装置及故障预测方法
公开(公告)号：US08489966B2
公开(公告)日：2013-07-16
申请号：US12986564
申请日：2011-01-07
申请人： Franz Michael Schuette , Lutz Filor
发明人： Franz Michael Schuette , Lutz Filor
IPC分类号： G11C29/00
CPC分类号： G11C29/00 , G06F11/0727 , G06F11/0751 , G11C29/52
摘要： A solid-state mass storage device and method of operating the storage device to anticipate the failure of at least one memory device thereof before a write endurance limitation is reached. The method includes assigning at least a first memory block of the memory device as a wear indicator that is excluded from use as data storage, using pages of at least a set of memory blocks of the memory device for data storage, writing data to and erasing data from each memory block of the set in program/erase (P/E) cycles, performing wear leveling on the set of memory blocks, subjecting the wear indicator to more P/E cycles than the set of memory blocks, performing integrity checks of the wear indicator and monitoring its bit error rate, and taking corrective action if the bit error rate increases.
摘要翻译：一种固态大容量存储装置和方法，用于在达到写入耐力限制之前操作存储装置以预测其至少一个存储器件的故障。该方法包括将存储器件的至少第一存储块分配为作为数据存储被排除的磨损指示符，使用用于数据存储的存储器件的至少一组存储器块的页面，将数据写入和擦除在程序/擦除（P / E）循环中来自该组的每个存储器块的数据，对该组存储器块执行磨损均衡，对磨损指示器进行比该组存储器块更多的P / E周期，执行完整性检查磨损指示器并监视其误码率，如果误码率增加，则采取纠正措施。

10. 发明授权

US08489855B2 NAND flash-based solid state drive and method of operation 有权
标题翻译：基于NAND闪存的固态驱动器和操作方法
公开(公告)号：US08489855B2
公开(公告)日：2013-07-16
申请号：US13103270
申请日：2011-05-09
申请人： Franz Michael Schuette
发明人： Franz Michael Schuette
IPC分类号： G06F12/06 , G06F12/08 , G11C16/10
CPC分类号： G06F12/0246 , G06F3/0616 , G06F3/064 , G06F3/0644 , G06F3/0652 , G06F3/0679 , G06F2212/7202 , G06F2212/7205 , G06F2212/7211
摘要： A solid state drive that uses over-provisioning of NAND flash memory blocks as part of housekeeping functionality, including deduplication and coalescence of data for efficient usage of NAND flash memory devices and maintaining sufficient numbers of erased blocks to promote write performance.
摘要翻译：一种固态驱动器，其使用NAND闪存块的过度供应作为内务管理功能的一部分，包括用于有效利用NAND闪速存储器件的数据的重复数据消除和聚合，并保持足够数量的擦除块来提升写入性能。

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